A 13bit,pipelined analog-to-digital converter （ADC） designed to achieve high linearity is described. The high linearity is realized by using the passive capacitor error-averaging technique to calibrate the capacitor...A 13bit,pipelined analog-to-digital converter （ADC） designed to achieve high linearity is described. The high linearity is realized by using the passive capacitor error-averaging technique to calibrate the capacitor mismatch error, a gain-boosting opamp to minimize the finite gain error and gain nonlinearity,a bootstrapping switch to reduce the switch on-resistor nonlinearity, and an anti-disturb design to reduce the noise from the digital supply. This ADC is implemented in 0.18μm CMOS technology and occupies a die area of 3.2mm^2 , including pads. Measured performance includes - 0.18/ 0.15LSB of differential nonlinearity, -0.35/0.5LSB of integral nonlinearity, 75.7dB of signal-to-noise plus distortion ratio （SNDR） and 90. 5 dBc of spurious-free dynamic range （SFDR） for 2.4MHz input at 2.5MS/s. At full speed conversion （5MS/s） and for the same 2.4MHz input, the measured SNDR and SFDR are 73.7dB and 83.9 dBc, respectively. The power dissipation including output pad drivers is 21mW at 2.5MS/s and 34mW at 5MS/s,both at 2.7V supply.展开更多
针对原边反馈反激变换器具有辅助绕组而成本偏高的问题,基于原边反馈与峰值电流控制方案,提出了一种基于开关管漏极反馈的反激变换器模型。与原边反馈反激变换器相比,漏极反馈反激变换器能够减少变压器辅助绕组,降低了成本,且具有较高...针对原边反馈反激变换器具有辅助绕组而成本偏高的问题,基于原边反馈与峰值电流控制方案,提出了一种基于开关管漏极反馈的反激变换器模型。与原边反馈反激变换器相比,漏极反馈反激变换器能够减少变压器辅助绕组,降低了成本,且具有较高的稳定性。首先,对此漏极反馈反激变换器模型进行了理论分析,并提出了一种高精度漏极采样方法。其次,基于开关网络模型法对工作在断续导通模式(Discontinuous conduction mode,DCM)下脉冲频率调制(Pulse frequency modulation,PFM)的漏极反馈反激变换器进行了小信号建模并进行补偿设计。通过Matlab/Simulink搭建模型验证其正确性;最后搭建试验平台来进行验证。结果表明,所提出的漏极反馈反激变换器模型是可行的。展开更多
An all-optical analog-to-digital converter capable of sampling at 50GS/s is described. The ADC works in the frequency domain. The RF signal is sampled by electro-optically steerable gratings and quantized by a set of ...An all-optical analog-to-digital converter capable of sampling at 50GS/s is described. The ADC works in the frequency domain. The RF signal is sampled by electro-optically steerable gratings and quantized by a set of detectors with scalable apertures.展开更多
This paper proposes the design and development of a novel, portable and low-cost intelligent electronic device (IED) for real-time monitoring of high frequency phenomena in CENELEC PLC band. A high speed floating-poin...This paper proposes the design and development of a novel, portable and low-cost intelligent electronic device (IED) for real-time monitoring of high frequency phenomena in CENELEC PLC band. A high speed floating-point digital signal processor (DSP) along with 4 MSPS analog-to-digital converter (ADC) is used to develop the intelligent electronic device. An optimized algorithm to process the analog signal in real-time and to extract the meaningful result using signal processing techniques has been implemented on the device. A laboratory environment has setup with all the necessary equipment including the development of the load model to evaluate the performance of the IED. Smart meter and concentrator is also connected to the low voltage (LV) network to monitor the PLC communication using the IED. The device has been tested in the laboratory and it has produced very promising results for time domain as well as frequency domain analysis. Those results imply that the IED is fully capable of monitoring high frequency disturbances in CENELEC PLC band.展开更多
为了满足测量领域对高质量恒流源的迫切需求,提出了一种基于STM32的便携式高精度0～24 m A恒流源的设计方案。由STM32微处理器控制高精度AD5062,实现V-I转换电路输入电压的精确调节,进而得到0～24 m A的输出电流。V-I转换电路由高性能...为了满足测量领域对高质量恒流源的迫切需求,提出了一种基于STM32的便携式高精度0～24 m A恒流源的设计方案。由STM32微处理器控制高精度AD5062,实现V-I转换电路输入电压的精确调节,进而得到0～24 m A的输出电流。V-I转换电路由高性能的运算放大器、精密的金属电阻等构成,其线性反馈调节电路使得输出电流更加稳定。实验结果表明,设计的恒流源最大标准差低于0.5μA,具有较高的精度。展开更多
文摘A 13bit,pipelined analog-to-digital converter （ADC） designed to achieve high linearity is described. The high linearity is realized by using the passive capacitor error-averaging technique to calibrate the capacitor mismatch error, a gain-boosting opamp to minimize the finite gain error and gain nonlinearity,a bootstrapping switch to reduce the switch on-resistor nonlinearity, and an anti-disturb design to reduce the noise from the digital supply. This ADC is implemented in 0.18μm CMOS technology and occupies a die area of 3.2mm^2 , including pads. Measured performance includes - 0.18/ 0.15LSB of differential nonlinearity, -0.35/0.5LSB of integral nonlinearity, 75.7dB of signal-to-noise plus distortion ratio （SNDR） and 90. 5 dBc of spurious-free dynamic range （SFDR） for 2.4MHz input at 2.5MS/s. At full speed conversion （5MS/s） and for the same 2.4MHz input, the measured SNDR and SFDR are 73.7dB and 83.9 dBc, respectively. The power dissipation including output pad drivers is 21mW at 2.5MS/s and 34mW at 5MS/s,both at 2.7V supply.
文摘针对原边反馈反激变换器具有辅助绕组而成本偏高的问题,基于原边反馈与峰值电流控制方案,提出了一种基于开关管漏极反馈的反激变换器模型。与原边反馈反激变换器相比,漏极反馈反激变换器能够减少变压器辅助绕组,降低了成本,且具有较高的稳定性。首先,对此漏极反馈反激变换器模型进行了理论分析,并提出了一种高精度漏极采样方法。其次,基于开关网络模型法对工作在断续导通模式(Discontinuous conduction mode,DCM)下脉冲频率调制(Pulse frequency modulation,PFM)的漏极反馈反激变换器进行了小信号建模并进行补偿设计。通过Matlab/Simulink搭建模型验证其正确性;最后搭建试验平台来进行验证。结果表明,所提出的漏极反馈反激变换器模型是可行的。
文摘An all-optical analog-to-digital converter capable of sampling at 50GS/s is described. The ADC works in the frequency domain. The RF signal is sampled by electro-optically steerable gratings and quantized by a set of detectors with scalable apertures.
文摘This paper proposes the design and development of a novel, portable and low-cost intelligent electronic device (IED) for real-time monitoring of high frequency phenomena in CENELEC PLC band. A high speed floating-point digital signal processor (DSP) along with 4 MSPS analog-to-digital converter (ADC) is used to develop the intelligent electronic device. An optimized algorithm to process the analog signal in real-time and to extract the meaningful result using signal processing techniques has been implemented on the device. A laboratory environment has setup with all the necessary equipment including the development of the load model to evaluate the performance of the IED. Smart meter and concentrator is also connected to the low voltage (LV) network to monitor the PLC communication using the IED. The device has been tested in the laboratory and it has produced very promising results for time domain as well as frequency domain analysis. Those results imply that the IED is fully capable of monitoring high frequency disturbances in CENELEC PLC band.
文摘为了满足测量领域对高质量恒流源的迫切需求,提出了一种基于STM32的便携式高精度0～24 m A恒流源的设计方案。由STM32微处理器控制高精度AD5062,实现V-I转换电路输入电压的精确调节,进而得到0～24 m A的输出电流。V-I转换电路由高性能的运算放大器、精密的金属电阻等构成,其线性反馈调节电路使得输出电流更加稳定。实验结果表明,设计的恒流源最大标准差低于0.5μA,具有较高的精度。
