Recess-free enhancement-mode AlGaN/GaN RF HEMTs on Si substrate

Enhancement-mode(E-mode)GaN-on-Si radio-frequency(RF)high-electron-mobility transistors(HEMTs)were fabri-cated on an ultrathin-barrier(UTB)AlGaN(<6 nm)/GaN heterostructure featuring a naturally depleted 2-D electron gas(2DEG)channel.The fabricated E-mode HEMTs exhibit a relatively high threshold voltage(VTH)of+1.1 V with good uniformity.A maxi-mum current/power gain cut-off frequency(fT/fMAX)of 31.3/99.6 GHz with a power added efficiency(PAE)of 52.47%and an out-put power density(Pout)of 1.0 W/mm at 3.5 GHz were achieved on the fabricated E-mode HEMTs with 1-μm gate and Au-free ohmic contact.

Theoretical Study on the Reaction of PCl_3/H_2 on Silicon Substrate Surface

The reaction mechanism of PCl3/H2 on silicon substrate surface （simulated by Si4 cluster） was investigated with Density Functional Theory （DFT） at the B3LYP/6-311G^＊＊ level. On silicon substrate, PCl3 firstly undergoes dissociative adsorption, and then the adsorption product reacts with H2 via a four-step multi-channel mode to give the final product PSi4 cluster. The geometries at each stationary point were fully optimized. The possible transition states were determined by vibrational mode analysis and IRC verification. And finally, the main reaction channel was given.

Substrate bias effects on collector resistance in SiGe heterojunction bipolar transistors on thin film silicon-on-insulator

An analytical expression for the co/lector resistance of a novel vertical SiGe heterojunction bipolar transistor （HBT） on thin film silicon-on-insulator （SOI） is obtained with the substrate bias effects being considered. The resistance is found to decrease slowly and then quickly and to have kinks with the increase of the substrate-collector bias, which is quite different from that of a conventional bulk HBT. The model is consistent with the simulation result and the reported data and is useful to the frequency characteristic design of 0.13 μtm millimeter-wave SiGe SOI BiCMOS devices.

Fabrication of seeded substrates for layer transferrable silicon films

The layer transfer process is one of the most promising methods for low-cost and highly-efficient solar cells, in which transferrable mono-crystalline silicon thin wafers or films can be produced directly from gaseous feed-stocks. In this work, we show an approach to preparing seeded substrates for layer-transferrable silicon films. The commercial silicon wafers are used as mother substrates, on which periodically patterned silicon rod arrays are fabricated, and all of the surfaces of the wafers and rods are sheathed by thermal silicon oxide. Thermal evaporated aluminum film is used to fill the gaps between the rods and as the stiff mask, while polymethyl methacrylate （PMMA） and photoresist are used as the soft mask to seal the gap between the filled aluminum and the rods. Under the joint resist of the stiff and soft masks, the oxide on the rod head is selectively removed by wet etching and the seed site is formed on the rod head. The seeded substrate is obtained after the removal of the masks. This joint mask technique will promote the endeavor of the exploration of mechanically stable, unlimitedly reusable substrates for the kerfless technology.

Breakdown characteristics of AlGaN/GaN Schottky barrier diodes fabricated on a silicon substrate

In this work, the breakdown characteristics of AlGaN/GaN planar Schottky barrier diodes （SBDs） fabricated on the silicon substrate are investigated. The breakdown voltage （BV） of the SBDs first increases as a function of the anodeto-cathode distance and then tends to saturate at larger inter-electrode spacing. The saturation behavior of the BV is likely caused by the vertical breakdown through the intrinsic GaN buffer layer on silicon, which is supported by the post-breakdown primary leakage path analysis with the emission microscopy. Surface passivation and field plate termination are found effective to suppress the leakage current and enhance the BV of the SBDs. A high BV of 601 V is obtained with a low on-resistance of 3.15 mΩ·cm^2.

Dielectric layer-dependent surface plasmon effect of metallic nanoparticles on silicon substrate

The electromagnetic interaction between Ag nanoparticles on the top of the Si substrate and the incident light has been studied by numerical simulations. It is found that the presence of dielectric layers with different thicknesses leads to the varied resonance wavelength and scattering cross section and consequently the shifted photocurrent response for all wavelengths. These different behaviours are determined by whether the dielectric layer is beyond the domain where the elcetric field of metallic plasmons takes effect, combined with the effect of geometrical optics. It is revealed that for particles of a certain size, an appropriate dielectric thickness is desirable to achieve the best absorption. For a certain thickness of spacer, an appropriate granular size is also desirable. These observations have substantial applications for the optimization of surface plasmon enhanced silicon solar cells.

A CMOS-compatible silicon substrate optimization technique and its application in radio frequency crosstalk isolation

In this paper, a complementary metal-oxide semiconductor （CMOS）-compatible silicon substrate optimization technique is proposed to achieve effective isolation. The selective growth of porous silicon is used to effectively suppress the substrate crosstalk. The isolation structures are fabricated in standard CMOS process and then this post-CMOS substrate optimization technique is carried out to greatly improve the performances of crosstalk isolation. Three-dimensional electro-magnetic simulation is implemented to verify the obvious effect of our substrate optimization technique. The morphologies and growth condition of porous silicon fabricated have been investigated in detail. Furthermore, a thick selectively grown porous silicon （SGPS） trench for crosstalk isolation has been formed and about 20dB improvement in substrate isolation is achieved. These results demonstrate that our post-CMOS SGPS technique is very promising for RF IC applications.

An Improved Room-Temperature Silicon Terahertz Photodetector on Sapphire Substrates

We design and fabricate a good performance silicon photoconductive terahertz detector on sapphire substrates at room temperature.The best voltage responsivity of the detector is 6679 V/W at frequency 300 GHz as well as low voltage noise of 3.8 nV/Hz1/2 for noise equivalent power 0.57 pW/Hz1/2.The measured response time of the device is about 9 μs,demonstrating that the detector has a speed of>110 kHz.The achieved good performance,together with large detector size(acceptance area is 3μm×160μm),simple structure,easy manufacturing method,compatibility with mature silicon technology,and suitability for large-scale fabrication of imaging arrays provide a promising approach to the development of sensitive terahertz room-temperature detectors.

SUBSTRATE EFFECT ON HYDROGENATED MICROCRYSTALLINE SILICON FILMS DEPOSITED WITH VHF-PECVD TECHNIQUE

Raman spectra and scanning electron microscope （SEM） techniques were used to determine the structural properties of microcrb＇stalline silicon （μc-Si：H） films deposited on different substrates with the very high frequency plasma-enhanced chemical vapor deposition （VHF-PECVD） technique. Using the Raman spectra, the values of crystalline volume fraction Xc and average grain size d are 86%, 12.3nm; 65%, 5.45nm; and 38%, 4.05nm, for single crystalline silicon wafer, coming 7059 glass, and general optical glass substrates, respectively. The SEM images further demonstrate the substrate effect on the film surface roughness. For the single crystalline silicon wafer and Coming 7059 glass, the surfaces of the μc-Si：H films are fairly smooth because of the homogenous growth or h＇ttle lattice mismatch. But for general optical glass, the surface of the μ-Si： H film is very rough, thus the growing surface roughness affects the crystallization process and determines the average grain size of the deposited material. Moreover, with the measurements of thickness, photo and dark conductivity, photosensitivity and activation energy, the substrate effect on the deposition rate, optical and electrical properties of the μc-Si：H thin films have also been investigated. On the basis of the above results, it can be concluded that the substrates affect the initial growing layers acting as a seed for the formation of a crystalline-like material and then the deposition rates, optical and electrical properties are also strongly influenced, hence, deposition parameter optimization is the key method that can be used to obtain a good initial growing layer, to realize the deposition of μc-Si：H films with device-grade quality on cheap substrates such as general glass.

Design of MEMS C-Band Microstrip Antenna Array Based on High-Resistance Silicon for Intelligent Ammunition

In recent years, microstrip antennas have been more widely applied in satellite communications, mobile phones, unmanned aerial vehicle （UAV）, and weapons. A micro-electro-mechanical systems-based （MEMS-based） high-resistance silicon C-band microstrip antenna array has been designed for the intelligent ammunition. The center frequency is 4.5 GHz. A cavity has been designed in substrate to reduce the dielectric constant of silicon and high-resistance silicon has been used as the material of substrate to improve the gain of antenna. It is very easy to be manufactured by using MEMS technology because of the improved structure of the antenna. The results show that the gain of the antenna is 8 dB and voltage standing wave ratio （VSWR） is less than 2 by the analysis and simulation in high freauencv structure simulator （HFSS）.

Selective growth of carbon nanotube on silicon substrates

The carbon nanotube (CNT) growth of iron oxide-deposited trench-patterns and the locally-ordered CNT arrays on silicon substrate were achieved by simple thermal chemical vapor deposition(STCVD) of ethanol vapor. The CNTs were uniformly synthesized with good selectivity on trench-patterned silicon substrates. This fabrication process is compatible with currently used semiconductor-processing technologies, and the carbon-nanotube fabrication process can be widely applied for the development of electronic devices using carbon-nanotube field emitters as cold cathodes and can revolutionize the area of field-emitting electronic devices. The site-selective growth of CNT from an iron oxide nanoparticle catalyst patterned were also achieved by drying-mediated self-assembly technique. The present method offers a simple and cost-effective method to grow carbon nanotubes with self-assembled patterns.

Observation of Multi-layer Film on Si Substrate

The microstructures of Si substrate/amorphous SiO2 layer/SOI Si layer / polycrystal Si layer / amorphous SiO2 layer / coarse grain Al electrode were studied by using cross-section transmission electron microscopy, scanning electron microscopy, and high resolution electron microscopy. The straightness of interface between amorphous SiO2 layer and Si substrate is in 2-3 atomic layer. The defects were seldom found in the active area of SOI Si layer, and can be effectively confined in defect entrainment regions. The defects observed in defect entrainment regions are subgrain boundaries, large angle boundaries and dislocations. The dislocation loops which are parallel to the interface and have images with lines of no contrast under two beam condition have been observed in the side of SOI Si layer. Polycrystal Si layer consists of columnar and fine grains without preferential orientation. An ultra-thin amorphous SiO2 layer exists between SOI Si layer and polycrystal Si layer.

The influence of an Si_xN_y interlayer on a GaN film grown on an Si(111) substrate

A method to drastically reduce dislocation density in a GaN film grown on an Si（111） substrate is newly developed. In this method, the SixNy interlayer which is deposited on an A1N buffer layer in situ is introduced to grow the GaN film laterally. The crack-free GaN film with thickness over 1.7 micron is successfully grown on an Si（lll） substrate. A synthesized GaN epilayer is characterized by X-ray diffraction （XRD）, atomic force microscope （AFM）, and Raman spectrum. The test results show that the GaN crystal reveals a wurtzite structure with the （0001） crystal orientation and the full width at half maximum of the X-ray diffraction curve in the （0002） plane is as low as 403 arcsec for the GaN film grown on the Si substrate with an SixNy interlayer. In addition, Raman scattering is used to study the stress in the sample. The results indicate that the SizNy interlayer can more effectively accommodate the strain energy. So the dislocation density can be reduced drastically, and the crystal quality of GaN film can be greatly improved by introducing an SixNy interlayer.

Design and Analysis of MEMS Based Aluminum Nitride (AlN), Lithium Niobate (LiNbO₃) and Zinc Oxide (ZnO) Cantilever with Different Substrate Materials for Piezoelectric Vibration Energy Harvesters Using COMSOL Multiphysics Software

Interest in energy harvesters has grown rapidly over the last decade. The cantilever shaped piezoelectric energy harvesting beam is one of the most employed designs, due to its simplicity and flexibility for further performance enhancement. The research effort in the MEMS Piezoelectric vibration energy harvester designed using three types of cantilever materials, Lithium Niobate (LiNbO3), Aluminum Nitride (AlN) and Zinc Oxide (ZnO) with different substrate materials: aluminum, steel and silicon using COMSOL Multiphysics package were designed and analyzed. Voltage, mechanical power and electrical power versus frequency for different cantilever materials and substrates were modeled and simulated using Finite element method (FEM). The resonant frequencies of the LiNbO3/Al, AlN/Al and ZnO/Al systems were found to be 187.5 Hz, 279.5 Hz and 173.5 Hz, respectively. We found that ZnO/Al system yields optimum voltage and electrical power values of 8.2 V and 2.8 mW, respectively. For ZnO cantilever on aluminum, steel and silicon substrates, we found the resonant frequencies to be 173.5 Hz, 170 Hz and 175 Hz, respectively. Interestingly, ZnO/steel yields optimal voltage and electrical power values of 9.83 V and 4.02 mW, respectively. Furthermore, all systems were studied at different differentiate frequencies. We found that voltage and electrical power have increased as the acceleration has increased.

X波段Si基片集成脊波导MEMS环行器

基于波导传输理论设计并制备了一款Si基片集成脊波导(RSIW)微电子机械系统(MEMS)环行器,该环形器以高阻硅作为衬底材料,采用高精度三维MEMS加工工艺制备而成。通过在基片集成波导(SIW)结构中添加脊梁结构,形成RSIW传输结构,使传输主模TE10模的截止频率比矩形波导TE10模的低,从而实现相同频率下更小的器件尺寸。同时,通过电磁仿真软件对射频匹配和磁场分布进行了精确的建模仿真,完成了Si基片集成脊波导MEMS环行器的仿真设计。制备了尺寸为6 mm×6 mm的环行器样品并进行了测试,结果验证了仿真设计的准确性,其工作频率为8~12 GHz,回波损耗大于20 dB,隔离度大于18 dB,插入损耗小于0.5 dB。实现优良微波特性的同时,相比于常规的SIW结构环行器尺寸缩小了20%左右。

n-nc-Si:H低温制备工艺及其在柔性钙钛矿太阳电池中的应用

【目的】为在低温工艺下制备出适用于柔性钙钛矿太阳电池的高性能电子传输层,需要对电子传输层材料及制备条件进行研究。【方法】将n型氢化纳米晶硅薄膜作为柔性钙钛矿太阳电池电子传输层,研究衬底温度对薄膜性能的影响,并优化电子传输层与钙钛矿层界面处理工艺和结构。【结果】得到暗电导率、光透过率、表面形貌适用于柔性钙钛矿太阳电池电子传输层的n型氢化纳米晶硅薄膜低温制备条件,经过界面优化处理的柔性钙钛矿太阳电池转换效率达到14.66%。【结论】在低温工艺下制备出了高性能的电子传输层及柔性钙钛矿太阳电池,对进一步开展叠层钙钛矿太阳电池的研究具有指导意义。

基于硅基堆叠SIP技术的超宽带T/R组件

传统的超宽带T/R组件采用的是两维砖块式结构,体积和重量已不适应目前小型化、低剖面、易共形的相控阵天线要求。文中提出的基于硅基堆叠系统级封装(SIP)技术,将四通道的射频芯片高度集成在硅基介质基板上,将多层介质基板厚金压合,实现多层堆叠的三维封装。通过采用芯片多功能集成技术和超宽带射频信号的垂直互连技术,设计出三维堆叠的四通道超宽带T/R组件。T/R组件带宽为6 GHz~18 GHz,单通道的发射功率优于23 dBm,接收增益优于20 dB,可实现6位数控衰减及6位数控移相,尺寸仅有13.0 mm×13.0 mm×3.4 mm。该技术可以实现多通道超宽带T/R组件的SIP封装,有利于工程应用。

X波段MEMS硅腔折叠基片集成波导环行器芯片

通信系统向小型化、高性能、集成化的快速发展对射频组件的体积和电性能提出了苛刻的要求。设计了一种X波段硅腔折叠基片集成波导(FSIW)环行器芯片。当基片集成波导(SIW)工作于主模时,将中央的对称面等效为虚拟磁壁,沿着窄边对电磁场进行多次折叠,形成FSIW。以该技术作为设计思路,提高空间利用率,实现了FSIW整体结构的小型化。将FSIW的优势融入环行器中心结设计,使设计的环行器芯片具有高功率容量、低插入损耗、体积小、质量轻的优点。基于微电子机械系统(MEMS)工艺,以高阻硅为衬底材料,制备了该硅腔FSIW环行器芯片,芯片整体尺寸为6.5 mm×6 mm×2.5 mm,工作频率为8.5~11.5 GHz,回波损耗>18.5 dB,带内插入损耗<0.4 dB,隔离度>20 dB。

空腔结构硅基载板封装的机械应力分析

基于硅基载板与芯片之间良好的热膨胀系数匹配性和硅通孔的高密度互联特性,硅基载板广泛应用于高集成度、高可靠微系统封装中。封装产品在工作过程中需要经受外界不同的加速度、随机振动、机械冲击以及环境温度变化、器件工作发热等引起的热应力,这些应力均可能引起封装发生分层、断裂等失效。因此,很有必要预测外界环境对封装可靠性的影响。本文以典型硅基载板封装为例,采用数值仿真方法研究封装在使用过程中外界机械应力和热应力对其可靠性的影响。结果表明,热应力对封装的变形和应力影响最大;随机振动频率50~2000 Hz范围和功率谱密度为4(m·s^(-2))^(2)/Hz内,封装不会产生共振失效;机械冲击载荷对封装影响最小。实际封装产品经过机械冲击和随机振动等试验验证,满足设定的使用要求。

一种考虑复合电流的SiC LBJT行为模型改进

介绍了一种考虑基区SiC/SiO2界面处复合电流的SiC LBJT改进模型。分析了横向碳化硅双极结型晶体管与其垂直结构之间的区别,将横向BJT的外延层和半绝缘机构等效为衬底电容。再引入一个平行于SiC BJT基极结的附加二极管来描述复合电流,以垂直SiC BJT的SGP模型为基础建立SiC LBJT行为模型。校准了LBJT模型的基区渡越时间,模型与实际器件的开关特性接近吻合。相较于未考虑复合电流的LBJT模型,改进后的模型输出特性曲线与实测数据精度误差较小。该模型可以较精确地描述受复合电流影响的LBJT器件行为。