This paper analyses the transient characteristics of high temperature CMOS inverters and gate circuits, and gives the computational formulas of their rise time, fall time and delay time. It may be concluded that the t...This paper analyses the transient characteristics of high temperature CMOS inverters and gate circuits, and gives the computational formulas of their rise time, fall time and delay time. It may be concluded that the transient characteristics of CMOS inverters and gate circuits deteriorate due to the reduction of carrier mobilities and threshold voltages of MOS transistors and the increase of leakage currents of MOS transistors drain terminal pn junctions. The calculation results can explain the experimental phenomenon.展开更多
Programmable photonic waveguide meshes can be programmed into many different circuit topologies and thereby provide a variety of functions.Due to the complexity of the signal routing in a general mesh,a particular syn...Programmable photonic waveguide meshes can be programmed into many different circuit topologies and thereby provide a variety of functions.Due to the complexity of the signal routing in a general mesh,a particular synthesis algorithm often only accounts for a specific function with a specific cell configuration.In this paper,we try to synthesize the programmable waveguide mesh to support multiple configurations with a more general digital signal processing platform.To show the feasibility of this technique,photonic waveguide meshes in different configurations(square,triangular and hexagonal meshes)are designed to realize optical signal interleaving with arbitrary duty cycles.The digital signal processing(DSP)approach offers an effective pathway for the establishment of a general design platform for the software-defined programmable photonic integrated circuits.The use of well-developed DSP techniques and algorithms establishes a link between optical and electrical signals and makes it convenient to realize the computer-aided design of optics–electronics hybrid systems.展开更多
Achieving spatiotemporal control of light at high speeds presents immense possibilities for various applications in communication,computation,metrology,and sensing.The integration of subwavelength metasurfaces and opt...Achieving spatiotemporal control of light at high speeds presents immense possibilities for various applications in communication,computation,metrology,and sensing.The integration of subwavelength metasurfaces and optical waveguides offers a promising approach to manipulate light across multiple degrees of freedom at high speed in compact photonic integrated circuit(PIC)devices.Here,we demonstrate a gigahertz-rate-switchable wavefront shaping by integrating metasurface,lithium niobate on insulator photonic waveguides,and electrodes within a PIC device.As proofs of concept,we showcase the generation of a focus beam with reconfigurable arbitrary polarizations,switchable focusing with lateral focal positions and focal length,orbital angular momentum light beams as well as Bessel beams.Our measurements indicate modulation speeds of up to the gigahertz rate.This integrated platform offers a versatile and efficient means of controlling the light field at high speed within a compact system,paving the way for potential applications in optical communication,computation,sensing,and imaging.展开更多
在数字芯片设计后端流程中,宏和标准单元的布局是一项耗时的工作,通过机器学习快速有效地提供解决方案能够加快芯片开发的周期,降低人工布局带来的风险;然而布局问题是一个多目标优化问题,目前大多数方法都注重在满足各项指标下最大化...在数字芯片设计后端流程中,宏和标准单元的布局是一项耗时的工作,通过机器学习快速有效地提供解决方案能够加快芯片开发的周期,降低人工布局带来的风险;然而布局问题是一个多目标优化问题,目前大多数方法都注重在满足各项指标下最大化减小线长,已换取时钟延迟的降低,忽略了其他指标仍然存在下降的空间,例如良好的拥塞指标有利于降低芯片散热和功耗;针对上述问题,设计一种新的带有密集型奖励函数的深度强化学习框架,将拥塞信息映射到图像中,给出新的特征嵌入模型对版图的全局信息进行多尺度提取,并引入图注意力网络捕获网表的连接关系,采用Advantage Actor Critic(A2C)算法更新策略函数,实现了数字版图的自动布局,并在公共的数字芯片网表基准上验证了该方法的有效性。展开更多
The IEEE Standard 1149.1 boundary scan (BS) implementation provides the internal access required for testing the digital printed circuit board (PCB). However, the integrity of the boundary scan test infrastructure sh...The IEEE Standard 1149.1 boundary scan (BS) implementation provides the internal access required for testing the digital printed circuit board (PCB). However, the integrity of the boundary scan test infrastructure should be tested first to guarantee the validation of the results of the rest functional test and diagnosis. This paper describes the fault models and test principles of the BS test access port (TAP) lines on PCBs. A test algorithm with high fault coverage and short time is then presented for the PCB on which all ICs are BS ones.展开更多
基金Supported by the National Native Science Foundation of China
文摘This paper analyses the transient characteristics of high temperature CMOS inverters and gate circuits, and gives the computational formulas of their rise time, fall time and delay time. It may be concluded that the transient characteristics of CMOS inverters and gate circuits deteriorate due to the reduction of carrier mobilities and threshold voltages of MOS transistors and the increase of leakage currents of MOS transistors drain terminal pn junctions. The calculation results can explain the experimental phenomenon.
文摘Programmable photonic waveguide meshes can be programmed into many different circuit topologies and thereby provide a variety of functions.Due to the complexity of the signal routing in a general mesh,a particular synthesis algorithm often only accounts for a specific function with a specific cell configuration.In this paper,we try to synthesize the programmable waveguide mesh to support multiple configurations with a more general digital signal processing platform.To show the feasibility of this technique,photonic waveguide meshes in different configurations(square,triangular and hexagonal meshes)are designed to realize optical signal interleaving with arbitrary duty cycles.The digital signal processing(DSP)approach offers an effective pathway for the establishment of a general design platform for the software-defined programmable photonic integrated circuits.The use of well-developed DSP techniques and algorithms establishes a link between optical and electrical signals and makes it convenient to realize the computer-aided design of optics–electronics hybrid systems.
基金supported by the National Key R&D Program of China(Grant No.2019YFA0705000)the National Natural Science Foundation of China(Grant Nos.12192251,12274134,12174186,and 62288101)+2 种基金the Science and Technology Commission of Shanghai Municipality(Grant No.21DZ1101500)the Shanghai Municipal Education Commission(Grant No.2023ZKZD35)the Shanghai Pujiang Program(Grant No.20PJ1403400)
文摘Achieving spatiotemporal control of light at high speeds presents immense possibilities for various applications in communication,computation,metrology,and sensing.The integration of subwavelength metasurfaces and optical waveguides offers a promising approach to manipulate light across multiple degrees of freedom at high speed in compact photonic integrated circuit(PIC)devices.Here,we demonstrate a gigahertz-rate-switchable wavefront shaping by integrating metasurface,lithium niobate on insulator photonic waveguides,and electrodes within a PIC device.As proofs of concept,we showcase the generation of a focus beam with reconfigurable arbitrary polarizations,switchable focusing with lateral focal positions and focal length,orbital angular momentum light beams as well as Bessel beams.Our measurements indicate modulation speeds of up to the gigahertz rate.This integrated platform offers a versatile and efficient means of controlling the light field at high speed within a compact system,paving the way for potential applications in optical communication,computation,sensing,and imaging.
文摘在数字芯片设计后端流程中,宏和标准单元的布局是一项耗时的工作,通过机器学习快速有效地提供解决方案能够加快芯片开发的周期,降低人工布局带来的风险;然而布局问题是一个多目标优化问题,目前大多数方法都注重在满足各项指标下最大化减小线长,已换取时钟延迟的降低,忽略了其他指标仍然存在下降的空间,例如良好的拥塞指标有利于降低芯片散热和功耗;针对上述问题,设计一种新的带有密集型奖励函数的深度强化学习框架,将拥塞信息映射到图像中,给出新的特征嵌入模型对版图的全局信息进行多尺度提取,并引入图注意力网络捕获网表的连接关系,采用Advantage Actor Critic(A2C)算法更新策略函数,实现了数字版图的自动布局,并在公共的数字芯片网表基准上验证了该方法的有效性。
文摘The IEEE Standard 1149.1 boundary scan (BS) implementation provides the internal access required for testing the digital printed circuit board (PCB). However, the integrity of the boundary scan test infrastructure should be tested first to guarantee the validation of the results of the rest functional test and diagnosis. This paper describes the fault models and test principles of the BS test access port (TAP) lines on PCBs. A test algorithm with high fault coverage and short time is then presented for the PCB on which all ICs are BS ones.
