High-Speed,Robust CMOS Dynamic Circuit Design

A novel circuit with a narrow pulse driving structure is proposed for enhancing the noise immunity and improving the performance of wide fan-in dynamic circuits. Also,an analytical mode that agrees well with simulations is presented for transistor sizing. Simulation results show that an improvement of up to 12% over the conventional technique at 1GHz is obtained with this circuit,which can run 1.6 times faster than the existing technique with the same noise immunity.

AN ANALYSIS METHOD FOR HIGH-SPEED CIRCUIT SYSTEMS

A new method for analyzing high-speed circuit systems is presented. The method adds transmission line end currents to the circuit variables of the classical modified nodal approach. Then the matrix equation describing high-speed circuit system can be formulated directly and analyzed conveniently for its normative form. A time-domain analysis method for transmission lines is also introduced. The two methods are combined together to efficiently analyze high-speed circuit systems having general transmission lines. Numerical experiment is presented and the results are compared with that calculated by Hspice.

Power supply arm protection scheme of high-speed railway based on wide-area current differential

When fault occurs on cross-coupling autotransformer(AT)power supply traction network,the up-line and down-line feeder circuit breakers in the traction substation trip at the same time without selectivity,which leads to an extended power failure.Based on equivalent circuit and Kirchhoff’s current law,the feeder current characteristic in the substation,AT station and sectioning post when T-R fault,F-R fault,and T-F fault occur are analyzed and their expressions are obtained.When the traction power supply system is equipped with wide-area protection measurement and control system,the feeder protection device in each station collects the feeder currents in other two stations through the wide-area protection channel and a wide-area current differential protection scheme based on the feeder current characteristic is proposed.When a short-circuit fault occurs in the power supply arm,all the feeder protection devices in each station receive the feeder currents with time stamp in other two stations.After data synchronous processing and logic judgment,the fault line of the power supply arm can be identified and isolated quickly.The simulation result based on MATLAB/Simulink shows that the power supply arm protection scheme based on wide-area current differential has good fault discrimination ability under different fault positions,transition resistances,and fault types.The verification of measured data shows that the novel protection scheme will not be affected by the special working conditions of the electrical multiple unit(EMU),and reliability,selectivity,and rapidity of relay protection are all improved.

Electromagnetic Analysis and Optimization of High-speed Maglev Linear Synchronous Motor Based on Field-circuit Coupling

High speed maglev train has become a new non-contact transportation mode mainly studied in recent years because of its non-sticking and high speed characteristics.Firstly,the finite element model of the long stator linear synchronous motor(LSM)is established based on the structure of the test prototype.After calculation,it is compared with the experimental data and verified.On this basis,a field-circuit coupling model based on inverter circuit is established,and the influence of carrier wave ratio change on the output characteristics of LSM is calculated and analyzed.Finally,the filter circuit is introduced into the field-circuit coupling model,and the influence of the filter circuit on the output characteristics of the LSM is compared and analyzed.

Sensitivity analysis of distributed parameter elements in high-speed circuit networks

This paper presents an analysis method, based on MacCormack＇s technique, for the evaluation of the time domain sensitivity of distributed parameter elements in high-speed circuit networks. Sensitivities can be calculated from electrical and physical parameters of the distributed parameter elements. The proposed method is a direct numerical method of time-space discretization and does not require complicated mathematical deductive process. Therefore, it is very convenient to program this method. It can be applied to sensitivity analysis of general transmission lines in linear or nonlinear circuit networks. The proposed method is second-order-accurate. Numerical experiment is presented to demonstrate its accuracy and efficiency.

Analysis of Temperature Rise in High-Speed Permanent Magnet Synchronous Traction Motors by Coupling the Equivalent Thermal Circuit Method and Computational Fluid Dynamics

To solve the problem of temperature rise caused by the high power density of high-speed permanent magnet synchronous traction motors,the temperature rise of various components in the motor is analyzed by coupling the equivalent thermal circuit method and computational fluid dynamics.Also,a cooling strategy is proposed to solve the problem of temperature rise,which is expected to prolong the service life of these devices.First,the theoretical bases of the approaches used to study heat transfer and fluid mechanics are discussed,then the fluid flow for the considered motor is analyzed,and the equivalent thermal circuit method is introduced for the calculation of the temperature rise.Finally,the stator,rotor loss,motor temperature rise,and the proposed cooling method are also explored through experiments.According to the results,the stator temperature at 50,000 r/min and 60,000 r/min at no-load operation is 68℃ and 76℃,respectively.By monitoring the temperature of the air outlets inside and outside the motor at different speeds,it is also found that the motor reaches a stable temperature rise after 65 min of operation.Coupling of the thermal circuit method and computational fluid dynamics is a strategy that can provide the average temperature rise of each component and can also comprehensively calculate the temperature of each local point.We conclude that a hybrid cooling strategy based on axial air cooling of the inner air duct of the motor and water cooling of the stator can meet the design requirements for the ventilation and cooling of this type of motors.

Design of a Low-Power CMOS LVDS I/O Interface Circuit

The paper presents the design and implementation of LVDS （low-voltage differential signaling） receiver circuit, fully compatible with LVDS standard. The proposed circuit is composed of the telescopic amplifier and the comparator with internal hysteresis. The receiver supports 3.5 Gbps data rate with 7.4 mA current at 1.8 V supply according to post-layout circuit simulations. The circuit has the power consumption of 13.1 MW. Comparing with the conventional circuit, the circuit is achieved to reduce the power consumption by 19.1% and the data rate by 14.3 %. The validity and effectiveness of the proposed circuit are verified through the circuit simulation with Samsung 0.18 μm CMOS （complementary metal-oxide-semiconductor） standard technology under the 1.8 V supply voltage.

Low-Power Digital Circuit Design with Triple-Threshold Voltage

Triple-threshold CMOS technique provides the transistors that have low-, normal-, and high-threshold voltage. This paper describes a low-power carry look-ahead adder with triple-threshold CMOS technique. While the low-threshold voltage transistors are used to reduce the propagation delay time in the critical path, the high-threshold voltage transistors are used to reduce the power consumption in the shortest path. Comparing with the conventional CMOS circuit, the circuit is achieved to reduce the power consumption by 14.71% and the power-delay-product by 16.11%. This circuit is designed with Samsung 0.35 um CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

Low-Power MCML Circuit with Sleep-Transistor

This paper proposes a low-power MOS current mode logic （MCML） circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to high-threshold voltage transistor to minimize the leakage current. The 16× 16 bit parallel multiplier is designed with the proposed technology. Comparing with the previous MCML circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/258. This circuit is designed with Samsung 0.35 um complementary metal oxide semiconductor （CMOS） process. The validity and effectiveness are verified through the HSPICE simulation.

Minimizing crosstalk for high-speed and high-density bus systems using the sample-decision method

This paper presents a method based on a sample-decision(SD) circuit to suppress crosstalk and noise for a high-speed and high-density bus system.A method to count the number of times of SD for different length of transmission lines is presented and a bit error rates(BERs) formula is given by the SD circuit.It is shown that for long transmission line systems,multiple SD circuits can improve the BERs significantly.Circuits simulation for single SD method is also done,it is found that when the amplitude peak values of the superposed crosstalk and noise are less than half of the corresponding signal ones,they will be eliminated completely for the cases investigated.

Design of low-offset low-power CMOS amplifier for biosensor application

A compacted and low-offset low-power CMOS am- plifier for biosensor application is presented in this paper. It includes a low offset Op-Amp and a high precision current reference. With a novel continuous-time DC offset rejection scheme, the IC achieves lower offset voltage and lower power consumption compared to previous designs. This configuration rejects large DC offset and drift that exist at the skin-electrode interface without the need of external components. The proposed amplifier has been implemented in SMIC 0.18-μm 1P6M CMOS technol-ogy, with an active silicon area of 100 μm by 120 μm. The back-annotated simulation results demonstrated the circuit features the systematic offset voltage less than 80 μV, the offset drift about 0.27 μV/℃ for temperature ranging from –30℃ to 100℃ and the total power dissipation consumed as low as 37.8 μW from a 1.8 V single supply. It dedicated to monitor low amplitude biomedical signals recording.

A low-power high-speed driving circuit for spatial light modulators

This paper describes the design and test of a novel custom driving circuit for multi-quantum-well （MQW） spatial light modulators（SLMs）.Unlike previous solutions,we integrated all blocks in one chip to synchronize the control logic circuit and the driving circuits.Single-slope digital-to-analog converters（DACs） inside each pixel are not adopted because it is difficult to eliminate capacitor mismatch.64 column-shared 8-bit resistor-string DACs are utilized to provide programmable output voltages from 0.5 to 3.8 V.They are located on the top of 64×64 driving pixels tightly to match each other with several dummies.Each DAC performs its conversion in 280 ns and draws 80μA.For a high speed data transfer rate,the system adopts a 2-stage shift register that operates at 50 MHz and the modulating rate achieves 50 K frames/s while dissipating 302 mW from a 5-V supply.The die is fabricated in a 0.35 /μm CMOS process and its area is 5.5 x 7 mm^2.

高速ADC电路的低功耗设计与优化技术

在当今信息时代,高速模数转换器(Analog-to-Digital Converter,ADC)在数字信号处理系统中扮演着至关重要的角色,其性能直接关系到系统的整体性能和功耗。文章研究了高速ADC电路的低功耗设计和优化问题,提出了一种在电路中通过降低静态功耗和动态功耗来实现低功耗目标的设计方法。该方法具体包括电源管理的优化、低功耗器件的采用和时钟分布的优化等技术手段。这种方法有效降低了电力消耗,同时提高了ADC性能,具有一定的实用意义。

New Design Methodologies for High Speed Low-Voltage 1-Bit CMOS Full Adder Circuits

New methodologies for l-Bit XOR-XNOR full- adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Simulation results illustrate the superiority of the proposed adder circuit against the conventional complementary metal-oxide-semiconductor （CMOS）, complementary pass-transistor logic （CPL）, TG, and Hybrid adder circuits in terms of delay, power and power delay product （PDP）. Simulation results reveal that the proposed circuit exhibits lower PDP and is more power efficient and faster when compared with the best available 1-bit full adder circuits. The design is implemented on UMC 0.18 μm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.

Performance Prospects of Fully-Depleted SOI MOSFET-Based Diodes Applied to Schenkel Circuit for RF-ID Chips

The feasibility of using the SOI-MOSFET as a quasi-diode to replace the Schottky-barrier diode in the Schenkel circuit is examined by device simulations primarily and experiments partly. Practical expressions of boost-up efficiency for d. c. condition and a. c. condition are proposed and are examined by simulations. It is shown that the SOI-MOSFET-based quasi-diode is a promising device for the Schenkel circuit because high boost-up efficiency can be gained easily. An a. c. analysis indicates that the fully-depleted condition should hold to suppress the floating-body effect for GHz-level RF applications of a quasi-diode.

Interruption Characteristics of High-speed Switches in 500 kV Fault Current Limiter with High Coupled Split Reactance

A 500 kV high-voltage AC fault current limiter(FCL)based on a high coupled split reactor(HCSR)is pro-posed by the National key R&D project team.Low impedance under normal conditions and high impedance under short-circuit conditions are accomplished by the cooperation of HCSR and high-speed switches.High-speed switches play an important role in current limiting processes,thus interruption characteristics of the high-speed switch in the 500 kV FCL are studied in this paper.The simulation model of the FCL and the external equivalent power grid are established.The short-circuit current and recovery voltage characteristics of the high-speed switch in FCL are simulated.The results show that maximum DC component of the short-circuit current of the high-speed switch reaches 91%,the maximum peak value is 118 kA,and the longest arcing time is 14.8 ms.There is a discontinuity in the curve of the short-circuit current peak and arcing time as a function of the short-circuit occurrence time;the peak recovery voltage of a single break of the high-speed switch has a maximum value of 87.5 kV under a three-phase ungrounded short-circuit condition,and the rate of rise of recovery voltage is o.22 kV/s.The recovery voltage peak shows a period change with the short-circuit occurrence time,and the period is 10 ms.The effects of the shunt capacitor value and short-circuit ground resistance on the recovery voltage of high-speed switching are also studied.The research can be used for reference by R&D personnel and testersof500kVFCLs.Index Terms-Fault current limiter(FCL),high coupled split reactor(HCSR),high-speed switch,interruption characteristics,short circuit current.

Gigahertz-rate-switchable wavefront shaping through integration of metasurfaces with photonic integrated circuit

Achieving spatiotemporal control of light at high speeds presents immense possibilities for various applications in communication,computation,metrology,and sensing.The integration of subwavelength metasurfaces and optical waveguides offers a promising approach to manipulate light across multiple degrees of freedom at high speed in compact photonic integrated circuit(PIC)devices.Here,we demonstrate a gigahertz-rate-switchable wavefront shaping by integrating metasurface,lithium niobate on insulator photonic waveguides,and electrodes within a PIC device.As proofs of concept,we showcase the generation of a focus beam with reconfigurable arbitrary polarizations,switchable focusing with lateral focal positions and focal length,orbital angular momentum light beams as well as Bessel beams.Our measurements indicate modulation speeds of up to the gigahertz rate.This integrated platform offers a versatile and efficient means of controlling the light field at high speed within a compact system,paving the way for potential applications in optical communication,computation,sensing,and imaging.

CMOS数字电路的速度功耗优化设计

在既定工艺条件下，改善电路性能可以通过改进电路、采用不同的时钟技术以及调整电路的器件尺寸来实现；改进电路，可以提高电路速度，减小或消除时钟偏差问题；选择适当的时钟技术，能够满足功耗、速度或可靠性等方面的不同要求；在优化程序的帮助下，调整器件尺寸能大大减小电路面积并改善电路性能。文中对以上几个方面进行理论分析和计算机模拟，得到有关高速ＣＭＯＳ电路的选择原则和设计方法。

MOS电流模逻辑加法器结构设计

为克服传统静态CMOS电路在高频工作时的缺陷,引入了MOS电流模逻辑(MOS Current Mode Logic,MCML)电路.MCML电路是一种差分对称结构逻辑电路,与传统的CMOS电路比较,在高频段工作时功耗相对较低,具有典型的高速低功耗特性.在对MCML电路的开关条件以及具有不同输入端的MCML逻辑门电路进行分析后,提出了实现MCML加法器的两种电路结构,并给出了不同结构的应用条件.仿真结果验证了电路结构设计的有效性.

一种GALS单通道协议自定时通信电路

本文提出了一种用于GALS(Globally Asynchronous Locally Synchronous)系统的单通道握手协议自定时通信电路,电路不需应答信号即可完成数据传输。在归零(return to zero)过程中加入了零协议逻辑(Null Convention Logic)门限门,使后向传输准延时不敏感;前向传输延迟小于2个门延时,优于传统的STFB(Single-track full buffer)电路和GasP电路。基于0.18μm CMOS工艺对不同温度下的电路功能和性能进行了仿真测试,10级串连情况下可允许发送端最高以2.56GHz的速度发送数据且功耗较低。此通信电路所具有的准延时不敏感和高速的特点使其可满足GALS应用的需求。