STUDY ON THE RELATION BETWEEN STRUCTURE AND HOT CARRIER EFFECT IMMUNITY FOR DEEP SUB-MICRON GROOVED GATE NMOSFET's

Grooved gate structure Metal-Oxide-Semiconductor (MOS) device is consideredas the most promising candidate used in deep and super-deep sub-micron region, for it cansuppress hot carrier effect and short channel effect deeply. Based on the hydrodynamic energytransport model, using two-dimensional device simulator Medici, the relation between structureparameters and hot carrier effect immunity for deep-sub-micron N-channel MOSFET's is studiedand compared with that of counterpart conventional planar device in this paper. The examinedstructure parameters include negative junction depth, concave corner and effective channel length.Simulation results show that grooved gate device can suppress hot carrier effect deeply even indeep sub-micron region. The studies also indicate that hot carrier effect is strongly influencedby the concave corner and channel length for grooved gate device. With the increase of concavecorner, the hot carrier effect in grooved gate MOSFET decreases sharply, and with the reducingof effective channel length, the hot carrier effect becomes large.

Switchable PLL Frequency Synthesizer andHot Carrier Effects

In this paper, a new strategy of switchable CMOS phase-locked loop frequency synthesizer is proposed to increase its tuning range. The switchable PLL which integrates two phase-locked loops with different tuning frequencies are designed and fabricated in 0.5 μm n-well CMOS process. Cadence/Spectre simulations show that the frequency range of the switchable phased-locked loop is between 320 MHz to 1.15 GHz. The experimental results show that the RMS jitter of the phase-locked loop changes from 26 ps to 123 ps as output frequency varies. For 700 MHz carrier frequency, the phase noise of the phase-locked loop reaches as low as ?81 dBc/Hz at 10 kHz offset frequency and ?104 dBc/Hz at 1 MHz offset frequency. A device degradation model due to hot carrier effects has been used to analyze the jitter and phase noise performance in an open loop voltage-controlled oscillator. The oscillation frequency of the voltage-controlled oscillator decreases by approximately 100 to 200 MHz versus the bias voltage and the RMS jitter increases by 40 ps under different phase-locked loop output frequencies after 4 hours of stress time.

Suppressing the hot carrier injection degradation rate in total ionizing dose effect hardened nMOSFETs

Annular gate nMOSFETs are frequently used in spaceborne integrated circuits due to their intrinsic good capability of resisting total ionizing dose （TID） effect. However, their capability of resisting the hot carrier effect （HCE） has also been proven to be very weak. In this paper, the reason why the annular gate nMOSFETs have good TID but bad HCE resistance is discussed in detail, and an improved design to locate the source contacts only along one side of the annular gate is used to weaken the HCE degradation. The good TID and HCE hardened capability of the design are verified by the experiments for I/O and core nMOSFETs in a 0.18 μm bulk CMOS technology. In addition, the shortcoming of this design is also discussed and the TID and the HCE characteristics of the replacers （the annular source nMOSFETs） are also studied to provide a possible alternative for the designers.

Oxide Thickness Effects on n-MOSFETs Under On-State Hot-Carrier Stress

Hot carrier induced (HCI) degradation of surface channel n MOSFETs with different oxide thicknesses is investigated under maximum substrate current condition.Results show that the key parameters m and n of Hu's lifetime prediction model have a close relationship with oxide thickness.Furthermore,a linear relationship is found between m and n .Based on this result,the lifetime prediction model can be expended to the device with thinner oxides.

Hot carrier effects of SOI NMOS

Hot carrier effect（HCE） is studied on annular NMOS and two-edged NMOS such as H-shape gate NMOS, T-shape gate NMOS and common two-edged NMOS.Based on the chemical reaction equation of HCE degradation and a geometry dependent reaction diffusion equation,a HCE degradation model for annular NMOS and two-edged NMOS is proposed.According to this model,we conclude that the time exponent of the threshold voltage degradation depends on the configuration of the gate,and annular NMOS has more serious HCE degradation than two-edged NMOS.The design,fabrication and HCE experiments of these NMOS in a 0.5-μm PD SOI process verify the correctness of the conclusion.

Effect of Hot Carrier on Amplitude Modulation and Demodulation of Gaussian High Power Helicon Wave in Homogeneous Longitudinally Magnetized Strain Dependent Dielectric Material

In the present communication, the hydrodynamic model is used to investigate the amplitude modulation as well as demodulation of an electromagnetic wave of high power helicon pump wave into another helicon wave in strain dependent dielectric material incorporating carrier heating (CH) effects. The consideration of CH in modulation and demodulation is prime importance for the adding of new dimension in analysis of amplification of acoustic helicon wave. By using the dispersion relation, threshold pump electric filed and growth rate of unstable mode from the modulation and demodulation of the high power helicon wave well above from the threshold value will be discussed in the present analysis. The numerical analysis is applied to a strain dependent dielectric material, BaTiO3 at room temperature and irradiated with high power helicon wave of frequency 1.78 × 1014 Hz. This material is very sensitive to the pump intensities, therefore during studies, Gaussian shape of the helicon pump wave is considered during the propagation in stain dependent dielectric material and opto-acoustic wave in the form of Gaussian profile (ω0,κ0) is induced longitudinally along the crystallographic plane of BaTiO3. Its variation is caused by the available magnetic field (ωc), interaction length (z) and pulsed duration of interaction (τ). From the analysis of numerical results, the incorporation of CH effect can effectively modify the magnitude of modulation or demodulation of the amplitude of high power helicon laser wave through diffusion process. Not only the amplitude modulation and demodulation of the wave, the diffusion of the CH effectively modifies the growth rate of unstable mode of frequency in BaTiO3. The propagation of the threshold electric field shows the sinusoidal or complete Gaussian profile, whereas this profile is found to be completely lost in growth of unstable mode. It has also been seen that the growth rate is observed to be of the order of 108 - 1010 s-1 but from diffusion of carrier heating, and that its order is enhanced from 1010 - 1012 s-1 with the variation of the magnetized frequency from 1 to 2.5 × 1014 Hz.

Unified Degradation Model in Low Gate Voltage Range During Hot-Carrier Stressing of p-MOS Transistors

Hot carrier effects of p MOSFETs with different oxide thicknesses are studied in low gate voltage range.All electrical parameters follow a power law relationship with stress time,but degradation slope is dependent on gate voltage.For the devices with thicker oxides,saturated drain current degradation has a close relationship with the product of gate current and electron fluence.For small dimensional devices,saturated drain current degradation has a close relationship with the electron fluence.This degradation model is valid for p MOSFETs with 0 25μm channel length and different gate oxide thicknesses.

New Forward Gated-Diode Technique for Separating Front Gate Interface- from Oxide-Traps Induced by Hot-Carrier-Stress in SOI-NMOSFETs

The front gate interface and oxide traps induced by hot carrier stress in SOI NMOSFETs are studied.Based on a new forward gated diode technique,the R G current originating from the front interface traps is measured,and then the densities of the interface and oxide traps are separated independently.The experimental results show that the hot carrier stress of front channel not only results in the strong generation of the front interface traps,but also in the significant oxide traps.These two kinds of traps have similar characteristic in increasing with the hot carrier stress time.This analysis allows one to obtain a clear physical picture of the effects of the hot carrier stress on the generating of interface and oxide traps,which help to understand the degradation and reliability of the SOI MOSFETs.

Hot carrier degradation and a new lifetime prediction model in ultra-deep sub-micron pMOSFET

The hot carrier effect （HCE） of an ultra-deep sub-micron p-channel metal–oxide semiconductor field-effect transistor （pMOSFET） is investigated in this paper. Experiments indicate that the generation of positively charged interface states is the predominant mechanism in the case of the ultra-deep sub-micron pMOSFET. The relation of the pMOSFET hot carrier degradation to stress time （t）, channel width （W ）, channel length （L）, and stress voltage （Vd ） is then discussed. Based on the relation, a lifetime prediction model is proposed, which can predict the lifetime of the ultra-deep sub-micron pMOSFET accurately and reflect the influence of the factors on hot carrier degradation directly.

Total dose irradiation and hot-carrier effects of sub-micro NMOSFETs

Total dose irradiation and the hot-carrier effects of sub-micro NMOSFETs are studied. The results show that the manifestations of damage caused by these two effects are quite different, though the principles of damage formation are somewhat similar. For the total dose irradiation effect, the most notable damage lies in the great increase of the off-state leakage current. As to the hot-carrier effect, most changes come from the decrease of the output characteristics curves as well as the decrease of trans-conductance. It is considered that the oxide-trapped and interface-trapped charges related to STI increase the current during irradiation, while the negative charges generated in the gate oxide, as well as the interface-trapped charges at the gate interface, cause the degradation of the hot-carrier effect. Different aspects should be considered when the device is generally hardened against these two effects.

Continuous analyticⅠ-Ⅴmodel for GS DG MOSFETs including hot-carrier degradation effects

We have studied the influence of hot-carrier degradation effects on the drain current of a gate-stack double-gate （GS DG） MOSFET device. Our analysis is carried out by using an accurate continuous current-voltage （I-V） model, derived based on both Poisson＇s and continuity equations without the need of charge-sheet approxi- mation. The developed model offers the possibility to describe the entire range of different regions （subthreshold, linear and saturation） through a unique continuous expression. Therefore, the proposed approach can bring consid- erable enhancement at the level of multi-gate compact modeling including hot-carrier degradation effects.

不同宽长比的柔性LTPS TFT的电应力可靠性

为了研究不同宽长比的柔性低温多晶硅薄膜晶体管(LTPS TFT)的电应力可靠性,测试了器件的I-V特性,以表征器件在强电场直流应力下由于自热效应和热载流子效应带来的电学性能退化。通过瞬态电流法表征了器件在强电场直流应力下的时间常数谱,并对其产生的新陷阱进行定位,分析了产生陷阱的内在机理。结果表明,在相同的强电场直流应力下宽长比为3/2.5的器件,其电学参数变化最大,自热效应以及热载流子效应带来的影响也最大。自热效应导致器件性能退化的主要原因是较大的栅源电压导致Si/SiO2界面处和栅氧化层中的陷阱增多,而热载流子效应导致器件性能退化的主要原因则是由于较大的漏源电压使得漏极晶界陷阱态密度急剧升高。

Hot-carrier effects on irradiated deep submicron NMOSFET

We investigate how F exposure impacts the hot-carrier degradation in deep submicron NMOSFET with different technologies and device geometries for the first time. The results show that hot-carrier degradations on irradiated devices are greater than those without irradiation, especially for narrow channel device. The reason is attributed to charge traps in STI, which then induce different electric field and impact ionization rates during hotcarrier stress.

基于HTO的LDMOS器件结构及其热载流子注入退化研究

为满足中低压消费电子的市场需求,小尺寸高密度Bipolar-CMOS-DMOS技术得到了蓬勃发展,低损耗和高可靠成为Bipolar-CMOS-DMOS技术中横向双扩散金属氧化物半导体场效应管(Lateral Double-diffused Metal-Oxide-Semiconductor field effect transistor,LDMOS)设计的重点和难点.本文介绍了一种基于高温氧化层(High Temperature Oxidation layer,HTO)结构的LDMOS,并对其热载流子注入退化机制进行了研究分析,利用高温氧化层结构改善了传统浅槽隔离(Shallow Trench Isolation,STI)结构中氧化物台阶嵌入半导体内部对器件热载流子注入造成的不利影响,提高器件可靠性,同时还缩短了器件导通情况下的电流路径长度,降低损耗.此外本文还提出了对P型体区的工艺优化方法,利用多晶硅作为高能量离子注入的掩蔽层,改善阱邻近效应对器件鲁棒性的影响,同时形成更深的冶金结,可以辅助漂移区杂质离子耗尽,降低漂移区表面电场,在不需要额外增加版次的情况下提高了器件击穿电压.最终得到的基于HTO结构的LDMOS击穿电压为43 V,比导通电阻为9.5 mΩ·mm^(2),线性区电流在10000 s之后的退化量仅为0.87%.

A Novel Empirical Model of I-V Characteristics for LDD MOSFET Including Substrate Current

A compact model for LDD MOSFET is proposed,which involves the hyperbolic tangent function description and the physics of device with emphasis on the substrate current modeling.The simulation results demonstrate good agreement with measurement,and show that deep submicron LDD MOSFET has larger substrate current than submicron device does.The improved model costs low computation consumption,and is effective in manifestation of hot carrier effect and other effects in deep submicron devices,in turn is suitable for design and reliability analysis of scaling down devices.

高可靠性P-LDMOS研究

分析了沟道高电场分布产生原因及各个参数对高电场的影响 ,提出了两条沟道设计的原则——拉长沟道同时降低沟道浓度 .模拟结果显示 ,两条原则能够有效地降低沟道两端的两个峰值电场 ,从而缓解沟道热载流子效应 ,提高 P- L DMOS的可靠性 .

深亚微米MOS器件的热载流子效应

对深亚微米器件中热载流子效应 (HCE)进行了研究 .还研究了沟道热载流子的产生和注入以及与器件工作在高栅压、中栅压和低栅压三种典型的偏置条件的关系 .在分析热载流子失效机理的基础上 ,讨论了热载流子效应对电路性能的影响 .提出影响晶体管热载流子效应的因素有 :晶体管的几何尺寸、开关频率、负载电容、输入速率及晶体管在电路中的位置 .通过对这些失效因素的研究并通过一定的再设计手段 ,可以减少热载流子效应导致的器件退化 .

MOSFET的热载流子效应及其表征技术

介绍了热载流子引起MOS器件退化的机制及其退化模型、最大应力模式和典型的寿命预测模型等,并对器件退化的表征技术进行了概述。

总剂量辐射对65 nm NMOSFET热载流子敏感参数的影响

为了研究总剂量辐射对纳米MOS晶体管热载流子效应的影响,对65nm体硅工艺的NMOS器件进行了总剂量辐射和热载流子试验,对比了辐射前后不同宽长比器件的跨导、栅极泄漏电流、线性饱和电流等电参数。结果表明,MOS器件的沟道宽度越窄,热载流子效应受辐射的影响越显著,总剂量辐射后热载流子效应对器件的损伤增强。分析认为,辐射在STI中引入的陷阱电荷是导致以上现象的主要原因。该研究结果为辐射环境下器件的可靠性评估提供了依据。

激光辐照下PV型HgCdTe探测器反常响应机理

利用PV型探测器开路电压的表达式,并考虑探测器的温度变化建立模型,对激光辐照下PV型HgCdTe探测器开路电压的变化进行了理论计算。当激光较弱时,计算结果与实验结果符合得很好。当激光较强时,对于辐照过程当中探测器输出变化的一般性趋势以及激光完全停照后的热弛豫过程,该模型也能给出较好的解释;但对于激光开始辐照时输出下跳和激光停止辐照时输出上跳的反常现象,该模型不能给出合理的解释。分析认为,该模型较好地描述了晶格温升对探测器输出的影响,但是它没有考虑热载流子效应;当激光较强时,热载流子效应不可忽略,特别是激光开始辐照和激光停止辐照时,载流子与晶格的温度差有比较明显的快速变化,从而导致了探测器的反常响应。