A calculation model for breakdown time delay and jitter of gas switches under hundred-nanosecond pulses and its application in a self-triggered pre-ionized switch

In this paper, a calculation model for the breakdown time delay and jitter of gas switches under hundred-nanosecond pulses is proposed and applied in a self-triggered pre-ionized switch. The effects of injection time of pre-ionization, pulse rise time, and the pre-ionization jitter are discussed and verified through experiments. It indicates that the pre-ionization should be injected when the electric field is high enough in the gap, injection after 80% peak-time can ensure its effectiveness.Then the statistical time delay jitter will be determined by the pre-ionization jitter, which is an intrinsic restriction of the self-triggered switch. However, when the changing rate of the pulsed electric field exceeds a certain value, the breakdown time delay jitter can be partly offset in the formative stage because the formative time delay has an exponential relationship with the electric field. Therefore, lower time jitter can be obtained under pulses with a shorter pulse rise time. In general, the results of the calculation model agree with the experimental results, and the experimental parameters which lead to a low jitter can also be used as a reference.

DELAY JITTER OF A PERIODIC CELL STREAM THROUGH AN ATM MULTIPLEXER IN A BURSTY TRAFFIC ENVIRONMENT

The periodic cell stream is a very important member among the input traffic sources in ATM networks. In this paper, a finite-buffered ATM multiplexer with traffic sources composed of a periodic cell stream, multiple i.i.d Bernoulli cell streams and bursty two-state Markov Modulated Bernoulli Process (MMBP) cell streams is exactly analyzed. The probability mass function of queuing delay, the autocorrelation and power spectrum of delay jitter for this periodic cell stream are derived. The analysis is used to expose the behavior of delay jitter for a periodic cell stream through an ATM multiplexer in a bursty traffic environment. The simulation results indicate that the analytical results are accurate.

Influences of Switching Jitter on the Operational Performances of Linear Transformer Drivers-Based Drivers

A whole circuit model of a linear transformer drivers （LTD） module composed of 60 cavities in series was developed in the software PSPICE to study the influence of switching jitter on the operational performances of LTDs. In the model, each brick in each cavity is capable of operating with jitter in its switch. Additionally, the manner of triggering cables entering into cavities was considered. The performances of the LTD module operating with three typical cavity-triggering sequences were simulated and the simulation results indicate that switching jitter affects slightly the peak and starting time of the output current pulse. However, the enhancement in switching jitter would significantly lengthen the rise time of the output current pulse. Without considering other factors, a jitter lower than 10 ns may be necessary for the switches in the LTD module to provide output current parameters with an acceptable deviation.

Employing Two ‘Sandwich Delay’ Mechanisms to Enhance Predictability of Embedded Systems Which Use Time-Triggered Co-Operative Architectures

In many real-time resource-constrained embedded systems, highly-predictable system behavior is a key design requirement. The “time-triggered co-operative” (TTC) scheduling algorithm provides a good match for a wide range of low-cost embedded applications. As a consequence of the resource, timing, and power constraints, the implementation of such algorithm is often far from trivial. Thus, basic implementation of TTC algorithm can result in excessive levels of task jitter which may jeopardize the predictability of many time-critical applications using this algorithm. This paper discusses the main sources of jitter in earlier TTC implementations and develops two alternative implementations – based on the employment of “sandwich delay” (SD) mechanisms – to reduce task jitter in TTC system significantly. In addition to jitter levels at task release times, we also assess the CPU, memory and power requirements involved in practical implementations of the proposed schedulers. The paper concludes that the TTC scheduler implementation using “multiple timer interrupt” (MTI) technique achieves better performance in terms of timing behavior and resource utilization as opposed to the other implementation which is based on a simple SD mechanism. Use of MTI technique is also found to provide a simple solution to “task overrun” problem which may degrade the performance of many TTC systems.

Sub-ns Jitter, 1ns Risetime and 10 kV Rectangular Pulse Trigger Generator

A new rectangular pulse trigger generator has been developed which can generate two 10 kV pulses with a risetime less than 1 ns, a jitter of 0.2 ns and a width of about 10 ns and 40 ns, respectively. This generator uses two polymer-foil switches and 25 ohm Blumlein transmission lines composed of two-parallel standard coaxial cables discharging into two 50 ohm output cables. The pulse width and the delay between two pulses can be adjusted by changing the length of the cables.

Development of a 4 MV Laser-Triggered Multi-Stage Switch

A 22-stage 4 MV laser-triggered multistage multi-channel switch （LTS） was designed according to the hypothesis that the well-proportioned electrical field distribution is helpful in reducing the jitter of delay. Field distribution in the switch section is regulated by a metal field regulation ring and several gradient rings. In order to reduce the jitter further, a SFB/N2 mixture is chosen as the switching medium. The generalized standard deviation of the self-breakdown voltage and the deviation of the average value from the prediction is less than 4.4% and 13% respectively. Linearity of the self-breakdown voltage is better than 0.95. Triggered by a laser pulse of 35 mJ/3 ns, the delay is about 26 ns at a working voltage of 85±3% USB （Self-breakdown Voltage）. Maximum deviation of delay is less than =t=2.5 ns. Jitter is less than 1.5 ns. The delay and jitter decrease with the increase in the working ratio （the ratio of working voltage to USB）, pressure or voltage.

Bus Arrival Time Prediction Based on Mixed Model

How to predict the bus arrival time accurately is a crucial problem to be solved in Internet of Vehicle. Existed methods cannot solve the problem effectively for ignoring the traffic delay jitter. In this paper,a three-stage mixed model is proposed for bus arrival time prediction. The first stage is pattern training. In this stage,the traffic delay jitter patterns(TDJP)are mined by K nearest neighbor and K-means in the historical traffic time data. The second stage is the single-step prediction,which is based on real-time adjusted Kalman filter with a modification of historical TDJP. In the third stage,as the influence of historical law is increasing in long distance prediction,we combine the single-step prediction dynamically with Markov historical transfer model to conduct the multi-step prediction. The experimental results show that the proposed single-step prediction model performs better in accuracy and efficiency than short-term traffic flow prediction and dynamic Kalman filter. The multi-step prediction provides a higher level veracity and reliability in travel time forecasting than short-term traffic flow and historical traffic pattern prediction models.

A Multi-Gap Multi-Channel Gas Switch for the Linear Transformer Driver

A multi-gap and multi-channel gas switch with convexo-convex discal planet electrodes was designed and investigated. Eight gaps are formed in series by a trigger electrode, six intermediate electrodes and two high voltage electrodes with a uniform gap length of 5 ram. The self breakdown and triggered breakdown performance of the switch are reported. Both the delay time and jitter decrease with the increase in the trigger voltage, switching coefficient and the decrease in the trigger isolating resistor. The delay time of the switch is about 40 ns, and the jitter is less than 2 ns when charged with 4-85 kV and triggered by a voltage pule of -75 kV. The inductance of the switch is about 30 nH.

Experimental Study on Triggering Characteristics of a Surface Flashover Triggered Vacuum Switch

Triggering characteristics of triggered vacuum switch （TVS）, including the discharge delay time, delay jitter, range of operational voltage and peak of pulsed current, are investigated. Both structure and experimental circuit of TVS are presented. The results indicate that TVS, as a surface flashover triggering device with high dielectric permittivity material, is with excellent triggering characteristics. When the hold-off voltage reaches 120 kV, the minimum operational voltage is 1.3 kV, and the minimum discharge delay time and jitter are 100 ns and ±10 ns, respectively. The peak current is up to 240 kA when the operational voltage reaches 100 kV. TVS can well satisfy the main demands of high voltage and current applications, and can also be used under a multi-crowbar circuit.

Analysis and Comparison of Five Kinds of Typical Device-Level Embedded Operating Systems

Today, the number of embedded system was applied in the field of automation and control has far exceeded a variety of general-purpose computer. Embedded system is gradually penetrated into all fields of human society, and ubiquitous embedded applications constitute the 'ubiquitous' computing era. Embedded operating system is the core of the em-bedded system, and it directly affects the performance of the whole system. Our Liaoning Provincial Key Laboratory of Embedded Technology has successfully developed five kinds of device-level embedded operating systems by more than ten years’ efforts, and these systems are Webit 5.0, Worix, μKernel, iDCX 128 and μc/os-II 128. This paper mainly analyses and compares the implementation mechanism and performance of these five kinds of device-level embedded operating systems in detail.

Joint Optimization of Communications and Computing Resources Allocation for Deterministic Transmission in Wireless Edge Networks

Motivated by 5th generation wireless systems(5G),a large number of emerging applications appear,which put forward higher requirements for the task’s transmission determinacy,which refers to the delay and jitter.To satisfy the deterministic requirement,mobile edge computing(MEC)is envisioned as a promising technique for reducing the end-to-end delay significantly.In this paper,we consider delaysensitive task and jitter-sensitive task,and then formulate the joint communications and computing optimization problem under the latency,the total bandwidth,the total transmission power of base station(BS)and the computing ability of the MEC server constraints to minimize the delay and jitter in a multiuser MEC system.Because of the problems are nonconvex,we decouple them into some subproblems and propose the corresponding algorithms to obtain a suboptimal solution.Finally,numerical results show that the proposed algorithms have a significant performance gain over the traditional solution in terms of the delay and the jitter.

A dynamic network Qo S control mechanism based on traffic prediction

A dynamic network Qo S control mechanism was proposed based on traffic prediction. It first predicts network traffic flow and then dynamically distributes network resources, which makes full use of network flow self-similarity and chaos. So it can meet changing network needs very well. The simulation results show that the dynamic Qo S control mechanism based on prediction has better network performance than that based on measurement.

Performance Evaluation of an Internet Protocol Security (IPSec) Based Multiprotocol Label Switching (MPLS) Virtual Private Network

This paper evaluates the performance of Internet Protocol Security (IPSec) based Multiprotocol Label Switching (MPLS) virtual private network (VPN) in a small to medium sized organization. The demand for security in data networks has been increasing owing to the high cyber attacks and potential risks associated with networks spread over distant geographical locations. The MPLS networks ride on the public network backbone that is porous and highly susceptible to attacks and so the need for reliable security mechanisms to be part of the deployment plan. The evaluation criteria concentrated on Voice over Internet Protocol (VoIP) and Video conferencing with keen interest in jitter, end to end delivery and general data flow. This study used both structured questionnaire and observation methods. The structured questionnaire was administered to a group of 70 VPN users in a company. This provided the study with precise responses. The observation method was used in data simulations using OPNET Version 14.5 Simulation software. The results show that the IPSec features increase the size of data packets by approximately 9.98% translating into approximately 90.02% effectiveness. The tests showed that the performance metrics are all well within the recommended standards. The IPSec Based MPLS Virtual private network is more stable and secure than one without IPSec.

海纳百川始雄浑 改善nForce2与USB设备的兼容性

如今的外设．包括键盘鼠标、闪盘、MP3播放器、DC、扫描仪等，几乎没有不支持USB接口的。遗憾的是目前大红大紫的nForce2主板具有一个通病——USB接口的兼容性不太好．一些USB设备无法在nForce2主板上正常使用．除了我们以前提到的USB接口的鼠标与键盘外．最容易与nForce2主板产生兼容性问题的外设是MP3播放器以及移动硬盘。

Finite-time Control for a Class of Networked Control Systems with Short Time-varying Delays and Sampling Jitter

This paper is concerned with the finite-time control problem for a class of networked control systems(NCSs) with short time-varying delays and sampling jitter.Considering a state feedback controller,the closed-loop NCS is described as a discrete-time linear system model,and the uncertain parts reflect the effect of the the network-induced delays and short sampling jitter of the system dynamics.Then a robust approach is proposed to solve the finite-time stability and stabilization problems for the considered NCS.An illustrative example is provided to demonstrate the effectiveness of the proposed theoretical results.

On-Chip Built-in Jitter Measurement Circuit for PLL Based on Duty-Cycle Modulation Vernier Delay Line

Phase-locked loops (PLLs) are essential wherever a local event is synchronized with a periodic external event. They are utilized as on-chip clock frequency generators to synthesize a low skew and higher internal frequency clock from an external lower frequency signal and its characterization and measurement have recently been calling for more and more attention. In this paper, a built-in on-chip circuit for measuring jitter of PLL based on a duty cycle modulation vernier delay line is proposed and demonstrated. The circuit employs two delay lines to measure the timing difference and transform the difference signal into digital words. The vernier lines are composed of delay cells whose duty cycle can be adjusted by a feedback voltage. It enables the circuit to have a self calibration capability which eliminates the mismatch problem caused by the process variation.

主控板内嵌于工控机的新型时序系统

可应用于大型物理实验及大规模科学工程中的时序系统已研制成功,其功能主板内嵌于一台工业控制机中,系统可输出多路时序脉冲,其周期、延时及脉宽均可步进调节。经一年多在线运行证实了该系统工作稳定可靠,定时脉冲前沿时间抖动小于5ns。详述了定时系统的软、硬件配置及运行实测结果。

On-Chip Multi-Giga Bit Cycle-to-Cycle Jitter Measurement Circuit

This paper presents an on-chip measurement circuit to measure multi-giga bit cycle-to-cycle jitter based on the vernier oscillator (VO), which is inherited from the famous vernier delay line. The calibration method is also given. The circuit adopts a differential digital controlled delay element, which makes the cir- cuit flexible in adjusting the measurement resolution, and a highly sensitive phase capturer, which makes the circuit able to measure jitters in pico-second range. The parallel structure makes it possible to measure consecutive cycle-to-cycle jitters. The performance of the circuit was verified via simulation with SMIC 0.18 μm process. During simulation under the clock with the period of 750 ps, the error between the measured RMS jitter and the theoretical RMS jitter was just 2.79 ps. Monte Carlo analysis was also conducted. With more advanced technology, the circuit can work better. This new structure can be implemented in chips as a built-in self-test IP core for testing jitter of PLL or other clocks.

Computational method for singularly perturbed delay differential equations of the reaction-diffusion type with negative shift

A numerical method for solving singularly perturbed delay differential equations with a layer or oscillatory behavior for which a small shift is introduced in the reaction term is presented.The stability and convergence of the method have been investigated.To demonstrate the efficiency of the method,two model examples have been presented.Numerical results obtained by the present scheme described that the finding of the present method is accurate than the findings of the previous studies.

Effect of chip rate on the ranging accuracy in a regenerative pseudo-noise ranging system

The ranging accuracy of a pseudo-noise ranging system is mainly decided by range jitter and time delay discrimination. Many factors can affect the ranging accuracy, one of which is the chip rate. In digital signal processing, the time delay discrimination and autocorrelation function of sampled ranging sequences of different chip rates are very different. An approximation simulation model is established according to an in-phase quadrature (I/Q) correlator which is used to evaluate the time delay. Simulation results of the range jitter and time delay discrimination show that the chip rate which provides a non-integer sample-to-chip rate ratio can achieve a higher ranging accuracy, and some test results validate the simulation model. In some design missions, the simulation results may help to select an optimum sample-to-chip rate ratio to satisfy the design requirement on the ranging accuracy.