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3D IC的热特性分析及预测
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作者 罗山焱 徐学良 +5 位作者 雷生吉 左江渝 张德 陈容 崔伟 陆科 《微电子学》 CAS 北大核心 2024年第4期665-670,共6页
3D IC器件通过三维堆叠技术显著提升了系统的集成度,增加了系统的功率密度,同时也带来了显著的热管理挑战。为了更好地对3D IC器件进行热分析,对3D IC进行结构建模,通过热路分析的方法对最高层芯片温度进行了估计,在此基础上考虑TSV结... 3D IC器件通过三维堆叠技术显著提升了系统的集成度,增加了系统的功率密度,同时也带来了显著的热管理挑战。为了更好地对3D IC器件进行热分析,对3D IC进行结构建模,通过热路分析的方法对最高层芯片温度进行了估计,在此基础上考虑TSV结构及不同TSV截面面积对芯片有源层温度的影响。最后,综合3D IC结构特征和热特性分析方法,基于MATLAB编写了3D IC的温度预测软件,并将该软件与商业COMSOL软件精度和效率对比,该软件优势在于,在满足一定的温度预测精度条件下,支持用户自定义3D IC的重要参数并迅速给出不同层芯片的温度预测和可视化表征,实现对不同的堆叠结构参数的3D IC器件进行快速地温度分析。 展开更多
关键词 硅通孔 3D IC 热特性
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深板层角膜移植与穿透性角膜移植治疗基质性角膜营养不良 被引量:3
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作者 Ahmed Reda 《国际眼科杂志》 CAS 北大核心 2020年第7期1118-1125,共8页
目的:比较深板层角膜移植(DALK)与穿透性角膜移植(PK)治疗基质性角膜营养不良的有效性和安全性。方法:系统回顾性Meta分析。对比较视力[最佳矫正视力(BCVA)(LogMAR)]和角膜内皮细胞计数(ECC)以及DALK和PK手术的安全性结果,包括移植物相... 目的:比较深板层角膜移植(DALK)与穿透性角膜移植(PK)治疗基质性角膜营养不良的有效性和安全性。方法:系统回顾性Meta分析。对比较视力[最佳矫正视力(BCVA)(LogMAR)]和角膜内皮细胞计数(ECC)以及DALK和PK手术的安全性结果,包括移植物相关结果和术中术后并发症。直到2019-06,使用Embase、PubMed和Google Scholar搜索符合条件的研究。结果:最终纳入了350例黄斑点状CD患者(男性59.71%)的五项对比研究。两种手术后的平均BCVA无明显差异。然而,经过DALK手术,术后两年角膜ECC明显升高(WMD=401.62 cell/mm2,95%CI:285.39-517.85,P<0.001),与接受PK手术的患者相比,移植物和内皮细胞排斥反应率显著降低(RR=0.30,95%CI:0.14-0.64,P=0.002;RR=0.09,95%CI:0.02-0.46,P=0.004)。但是,DALK手术增加了术中后弹力膜穿孔和术后双前房的风险(P<0.001)。结论:对于间质性CDs患者,DALK治疗在随访期间相对更有效,更安全,减少排斥反应,提高视觉效果。 展开更多
关键词 CDS 深板层角膜移植 穿透性角膜移植 ic3d
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3D IC中全铜互连热应力分析
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作者 王志敏 黄秉欢 +2 位作者 叶贵根 李逵 巩亮 《微电子学与计算机》 2023年第1期97-104,共8页
三维集成电路(Three-Dimensional Integrated Circuit,3D IC)技术相比于二维封装形式具有互连长度短、异构集成度高、功耗低以及封装尺寸小等特点.因为铜基体具有优异的导电性、抗电迁移性和机械性能,全铜互联结构替代了焊球作为连接结... 三维集成电路(Three-Dimensional Integrated Circuit,3D IC)技术相比于二维封装形式具有互连长度短、异构集成度高、功耗低以及封装尺寸小等特点.因为铜基体具有优异的导电性、抗电迁移性和机械性能,全铜互联结构替代了焊球作为连接结构应用于3D IC中.本文通过数值模拟研究了含有全铜互连和微流道结构的3D IC模型在循环温度载荷下的热可靠性,分析了全铜互联高度对模型内部热应力的影响.结果表明,全铜互连部分的最大热应力与铜柱所处的空间位置相关,离模型中心越远,铜柱内的变形越大.同时,最危险铜柱内部应力分布和变形情况表明,由于铜柱上下端面所受载荷性质不同,铜柱在热载荷作用下的Mises应力大致呈左右及上下对称分布.这会导致铜柱的潜在失效模式是轴向压缩和剪切共同作用下的断裂或损伤.另外,最大Mises应力随铜柱高度的增加而逐渐减小,当铜柱高度为300 gm时最大Mises应力趋于稳定,可以为全铜互连可靠性设计提供参考. 展开更多
关键词 3D IC 全铜互连 热应力 有限元模拟
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An optimal stacking order for mid-bond testing cost reduction of 3D IC 被引量:2
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作者 Ni Tianming Liang Huaguo +4 位作者 Nie Mu Bian Jingchang Huang Zhengfeng Xu Xiumin Fang Xiangsheng 《Journal of Southeast University(English Edition)》 EI CAS 2018年第2期166-172,共7页
In order to solve the problem that the testing cost of the three-dimensional integrated circuit(3D IC)is too high,an optimal stacking order scheme is proposed to reduce the mid-bond test cost.A new testing model is bu... In order to solve the problem that the testing cost of the three-dimensional integrated circuit(3D IC)is too high,an optimal stacking order scheme is proposed to reduce the mid-bond test cost.A new testing model is built with the general consideration of both the test time for automatic test equipment(ATE)and manufacturing failure factors.An algorithm for testing cost and testing order optimization is proposed,and the minimum testing cost and optimized stacking order can be carried out by taking testing bandwidth and testing power as constraints.To prove the influence of the optimal stacking order on testing costs,two baselines stacked in sequential either in pyramid type or in inverted pyramid type are compared.Based on the benchmarks from ITC 02,experimental results show that for a 5-layer 3D IC,under different constraints,the optimal stacking order can reduce the test costs on average by 13%and 62%,respectively,compared to the pyramid type and inverted pyramid type.Furthermore,with the increase of the stack size,the test costs of the optimized stack order can be decreased. 展开更多
关键词 three-dimensional integrated circuit(3D IC) mid-bond test cost stacking order sequential stacking failed bonding
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3D IC-TSV技术的散热特性研究 被引量:1
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作者 李丹 刘四平 +2 位作者 黄立恒 韩玥鸣 武艺宁 《环境技术》 2023年第6期54-60,共7页
基于3D IC—TSV互连技术,提出了考虑硅通孔的温度解析模型,Matlab分析表明:在芯片堆叠层数及芯片工作状态相同的情况下,考虑硅通孔之后的芯片温度比未考虑硅通孔时要低;在通孔直径不变的情况下,最高层芯片温度随间距P的增大而增大;在间... 基于3D IC—TSV互连技术,提出了考虑硅通孔的温度解析模型,Matlab分析表明:在芯片堆叠层数及芯片工作状态相同的情况下,考虑硅通孔之后的芯片温度比未考虑硅通孔时要低;在通孔直径不变的情况下,最高层芯片温度随间距P的增大而增大;在间距P不变的情况下,最高层芯片的温度随通孔直径D的减小而增大。通过热分析软件Icepak件对模型进行仿真,所得结果与Matlab仿真结果相对比,误差相差甚小,充分说明了硅通孔对芯片散热的有效性。 展开更多
关键词 3D IC 硅通孔 温度模型 最高层芯片 Icepak
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AIR-GAP-BASED RF COAXIAL TSV AND ITS CHARACTERISTIC ANALYSIS 被引量:1
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作者 Yu Le Sun Jiabin +3 位作者 Zhang Chunhong Wang Zhaoxin Zhang Chao Yang Haigang 《Journal of Electronics(China)》 2013年第6期587-598,共12页
Many 3D IC applications such as MEMS and RF systems require Through-Silicon Via (TSV) with operations for high-speed vertical communication. In this paper, we introduce a novel air-gap coaxial TSV that is suiTab, fo... Many 3D IC applications such as MEMS and RF systems require Through-Silicon Via (TSV) with operations for high-speed vertical communication. In this paper, we introduce a novel air-gap coaxial TSV that is suiTab, for such RF applications. Firstly, the detailed fabrication process is described to explain how to acquire such a structure. Then, an Resistor Inductance Conductance Capacitance (RLGC) model is developed to profile the transverse electromagnetic field effect of the proposed air-gap TSV. The model is further verified by a 3D field solver program through the S-parameter comparison. With reference to the numerically simulated results, this analytical model delivers a maximum deviation of less than 6%0, on the conditions of varying diameters, outer to inner radius ratios, and SU-8 central angles, etc. Taking advantages of scalability of the model, a number of air-gap-based TSV designs are simulated, providing 1.6-4.0 times higher bandwidth than the con- ventional coaxial TSVs and leading to an efficient high frequency vertical RF interconnection solution for 3D ICs. 展开更多
关键词 Through-Silicon Via (TSV) Three dimensional Integrated Circuits (3D IC) Air-gap COAXIAL Radio Frequency-Interconnect (RF-I)
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3D集成晶圆键合装备现状及研究进展 被引量:14
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作者 王成君 胡北辰 +1 位作者 杨晓东 武春晖 《电子工艺技术》 2022年第2期63-67,共5页
硅基异构集成和三维集成可满足电子系统小型化高密度集成、多功能高性能集成、小体积低成本集成的需求,有望成为下一代集成电路的使能技术,是集成电路领域当前和今后新的研究热点。硅基三维集成微系统可集成化合物半导体、CMOS、MEMS等... 硅基异构集成和三维集成可满足电子系统小型化高密度集成、多功能高性能集成、小体积低成本集成的需求,有望成为下一代集成电路的使能技术,是集成电路领域当前和今后新的研究热点。硅基三维集成微系统可集成化合物半导体、CMOS、MEMS等芯片,充分发挥不同材料、器件和结构的优势,可实现传统组件电路的芯片化、不同节点逻辑集成电路芯片的集成化,从而提升信号处理等电子产品的性价比。梳理了晶圆键合装备的工艺过程、主要厂商及市场需求、我国晶圆键合设备研发现状,并展望了晶圆键合设备的技术发展趋势。 展开更多
关键词 晶圆键合 异构集成 3D IC 共晶键合 直接键合 混合键合
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类同轴TSV的高频电学模型与分析 被引量:1
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作者 吴伟 孙毅鹏 +3 位作者 张兆华 王一丁 付永启 崔凯 《半导体技术》 CAS 北大核心 2022年第11期926-932,共7页
类同轴硅通孔(TSV)是射频三维(3D)集成电路(IC)中常用的垂直互连传输结构。针对该结构提出了一套通用的电阻-电感-电容-电导(RLCG)寄生参数计算公式,以及对应的高频等效电路模型。寄生参数是结构尺寸和材料特性的函数,可以方便地用于预... 类同轴硅通孔(TSV)是射频三维(3D)集成电路(IC)中常用的垂直互连传输结构。针对该结构提出了一套通用的电阻-电感-电容-电导(RLCG)寄生参数计算公式,以及对应的高频等效电路模型。寄生参数是结构尺寸和材料特性的函数,可以方便地用于预测电学性能。使用三维全波仿真软件对所提出的模型进行了高达100 GHz的仿真验证,并分析了模型的散射参数与结构尺寸之间的关系。最后提出了特征阻抗的计算和优化方法,该方法可以为类同轴TSV的参数的确定提供参考。 展开更多
关键词 三维(3D)集成电路(IC) 硅通孔(TSV) 类同轴结构 等效电路模型 电阻-电感-电容-电导(RLCG)参数
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三维集成电路中硅通孔电阻参数计算解析式提取的研究
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作者 鞠艳杰 《电路与系统》 2020年第3期55-60,共6页
硅通孔技术是三维集成电路实现层间垂直互连的关键,使三维集成电路具有连线短、尺寸小、功耗低、可异构等优点。作为三维集成电路中互连的硅通孔,其寄生参数的提取将直接影响到集成电路功耗,时延,噪声等方面的性能,因此硅通孔寄生参数... 硅通孔技术是三维集成电路实现层间垂直互连的关键,使三维集成电路具有连线短、尺寸小、功耗低、可异构等优点。作为三维集成电路中互连的硅通孔,其寄生参数的提取将直接影响到集成电路功耗,时延,噪声等方面的性能,因此硅通孔寄生参数提取对高性能芯片的成功设计具有十分重要意义。本文以高面率比圆柱硅通孔为研究对象,通过对不同尺寸参数下的圆柱硅通孔进行仿真,得到其电阻参数值,使用电磁场理论、曲线拟合方法,推导出高精度的电阻参数提取解析式。解析式可快速准确计算硅通孔的电阻参数值,大大提高了参数提取效率。 展开更多
关键词 TSV 3D IC 参数提取
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Challenges and prospects for advanced packaging
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作者 Zhiwen Chen Jiaju Zhang +1 位作者 Shizhao Wang Ching-Ping Wong 《Fundamental Research》 CSCD 2024年第6期1455-1458,共4页
In the post-Moore era,advanced packaging is becoming more critical to meet the everlasting demands of elec-tronic products with smaller size,more powerful performance and lower cost.In this paper,developments in advan... In the post-Moore era,advanced packaging is becoming more critical to meet the everlasting demands of elec-tronic products with smaller size,more powerful performance and lower cost.In this paper,developments in advanced packaging have been discussed,such as 3D IC packaging,fan-out packaging,and chiplet packaging.Insights on the major advantages and challenges have also been briefly introduced.Our prospects about the solu-tions to some fundamental issues in sustainable development of advanced packaging have also been elucidated.The critical aspects and opportunities lie in standardization,co-design tools,new handling technologies,as well as multi-scale modeling and simulation. 展开更多
关键词 Advanced packaging Wafer-level packaging 3D IC packaging Fan-out packaging Chiplet packaging Challenges and opportunities
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A transmission line-type electrical model for tapered TSV considering MOS effect and frequency-dependent behavior 被引量:3
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作者 刘松 单光宝 +1 位作者 谢成民 杜欣荣 《Journal of Semiconductors》 EI CAS CSCD 2015年第2期92-98,共7页
The analytical model of voltage-controlled MOS capacitance of tapered through silicon via (TSV) is derived. To capture the frequency-dependent behavior of tapered TSV, the conventional analytical equations of RLCG f... The analytical model of voltage-controlled MOS capacitance of tapered through silicon via (TSV) is derived. To capture the frequency-dependent behavior of tapered TSV, the conventional analytical equations of RLCG for two-wire transmission lines are revised. With the adoption of MOS capacitance model and the revised RLCG analytical equations, a transmission line-type electrical model for tapered TSV is proposed finally. All the proposed models are validated by simulation tools, and a good correlation is obtained between the proposed models and simulations up to 100 GHz. With the proposed model, both the semiconductor phenomenon and frequency- dependent behavior of tapered TSV can be fully captured at high frequency, and the performance of tapered TSV can be evaluated accurately and conveniently prior to 3D IC design. 展开更多
关键词 3D IC TSV TSV electrical model MOS effect transmission line
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An efficient method for comprehensive modeling and parasitic extraction of cylindrical through-silicon vias in 3D ICs 被引量:1
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作者 姚蔷 叶佐昌 喻文健 《Journal of Semiconductors》 EI CAS CSCD 2015年第8期150-156,共7页
To build an accurate electric model for through-silicon vias (TSVs) in 3D integrated circuits (ICs), a resistance and capacitance (RC) circuit model and related efficient extraction technique are proposed. The c... To build an accurate electric model for through-silicon vias (TSVs) in 3D integrated circuits (ICs), a resistance and capacitance (RC) circuit model and related efficient extraction technique are proposed. The circuit model takes both semiconductor and electrostatic effects into account, and is valid for low and medium signal frequencies. The electrostatic capacitances are extracted with a floating random walk based algorithm, and are then combined with the voltage-dependent semiconductor capacitances to form the equivalent circuit. Compared with the method used in Synopsys's Sdevice, which completely simulates the electro/semiconductor effects, the proposed method is more efficient and is able to handle the general TSV layout as well. For several TSV structures, the experimental results validate the accuracy of the proposed method for the frequency range from l0 kHz to 1 GHz. The proposed method demonstrated 47× speedup over the Sdevice for the largest 9-TSV case. 展开更多
关键词 3D IC through silicon via (TSV) parasitic extraction floating random walk algorithm metal-oxide- semiconductor (MOS) capacitance
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Circuit modeling and performance analysis of SWCNT bundle 3D interconnects
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作者 钱利波 朱樟明 +1 位作者 丁瑞雪 杨银堂 《Journal of Semiconductors》 EI CAS CSCD 2013年第9期171-177,共7页
Metallic carbon nanotubes (CNTs) have been proposed as a promising alternative to Cu interconnects in future integrated circuits (ICs) for their remarkable conductive, mechanical and thermal properties. Compact eq... Metallic carbon nanotubes (CNTs) have been proposed as a promising alternative to Cu interconnects in future integrated circuits (ICs) for their remarkable conductive, mechanical and thermal properties. Compact equiv alent circuit models for single-walled carbon nanotube (SWCNT) bundles are described, and the performance of SWCNT bundle interconnects is evaluated and compared with traditional Cu interconnects at different interconnect levels for through-silicon-via-based three dimensional (3D) ICs. It is shown that at a local level, CNT interconnects exhibit lower signal delay and smaller optimal wire size. At intermediate and global levels, the delay improvement becomes more significant with technology scaling and increasing wire lengths. For 1 mm intermediate and 10 mm global level interconnects, the delay of SWCNT bundles is only 49.49% and 52.82% that of the Cu wires, respec tively. 展开更多
关键词 three-dimensional integrated circuits (3D ICs) carbon nanotube (CNT) signal delay repeater inser-tion
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