元宇宙视域下的IP运营研究:概念层次、风险机制和口碑传播

元宇宙的出现推动了文化数字化的进程,通过整理相关文献可以看出,现有的IP研究依旧存在若干理论缺口。首先,鲜有研究针对IP具体提炼出其在运营过程中存在的风险机制,以及对口碑造成的影响。其次,目前研究也依旧缺乏对IP的概念化讨论。因此,对在元宇宙视域下IP运营和概念化的深化研究十分必要。使用深入访谈法,访谈了35名IP粉丝,IP概念的三个层次得以提炼,包括作为基础的知识产权、延伸的文化品牌和进阶的元宇宙。同时探讨了在元宇宙时代,IP运营中出现的风险机制和口碑传播机制。

Design of IP core for IIC bus controller based on FPGA

The intellectual property （IP） core for inter-integrated circuit （IIC） bus controller is designed using finite state machine （FSM） based on field programmable gate array （FPGA）. Not only the data from AT 24C02C can be read automatically after power on, but also the data from upper computer can be written into AT24C02C immediately under the control of the IIC bus controller. When it is applied to blast wave overpressure test system, the IIC bus controller can read and store working parameters automatically. In a laboratory environment, the IP core simulation is carried out and the result is accurate. In the explosion field test, by analyzing the obtained valid data, it can be concluded that the designed IP core has good reliability.

Integration and verification case of IP-core based system on chip design

In this paper, the design and verification process of an automobile-engine-fan control system on chip （SoC） are introduced. The SoC system, SHU-MV08, reuses four new intellectual property （IP） cores and the design flow is accomplished with 0.35 btm chartered CMOS technology. Some special functions of IP cores, the detailed integration scheme of four IP cores, and the verification method of the entire SoC are presented. To settle the verification problems brought by analog IP cores, NanoSim based chip-level mixed-signal verification method is introduced. The verification time is greatly reduced and the first tape-out achieves success which proves the validity of our design.

Design of IP core based on AMBA bus

With the rapid development of integrated circuit(IC)technology,reusable intelligent property(IP)core design is widely valued by the industry.Based on the in-depth study of the functional characteristics of advanced microcontroller bus architecture(AMBA),a design scheme of IP core is presented,and it is divided into the functional modules,and the structural design of the IP core is completed.The relationship between the internal modules of the IP core is clarified,and the top-down design method is used to build the internal architecture of the IP core.The IP core interface module,register module,baud rate module,transmit module,receive module,and interrupt module are designed in detail by using Verilog language.The simulation results show that the designed IP core supports serial peripheral interface(SPI)protocol,the function coverage of IP core reaches 100%,the maximum working frequency reaches 200 MHz,and the resource occupancy rate is less than 15%.The reusable IP core can support multiple data formats,multiple timing transmission modes,and master/slave operation modes,reducing the resource consumption of hardware circuits and having stronger applicability.

纳米继电器

当前微机保护将传统物理继电器抽象为继电保护算法逻辑,以软件实现继电器功能,其顺序执行、串行处理的程序调用方式难以适应新型电力系统故障态下电力电子设备继电保护微秒级动态响应特性要求。为此,提出基于芯片内纳米级电路构建的快速继电保护基础元件——纳米继电器,发明了专用纳米继电器IP(intellectual property)核硬件电路,代替现有微机保护串行算法,通过并行处理提高继电保护的处理能力和动作速度。设计特殊指令加速和多路指令集并发的架构,突破软件中断响应处理限制,以IP核的方式实现算法的固化封装,实现算法和逻辑的分离。给出纳米继电器的结构、功能分类以及处理模式与应用场景,分析纳米继电器的关键技术,并与传统继电器进行比较,阐述将其集成于保护装置的工程应用,最后展望纳米继电器未来的研究方向。

Spear and Shield： Evolution of Integrated Circuit Camouflaging

Intellectual property （IP） protection is one of the hardcore problems in hardware security. Semiconductor industry still lacks effective and proactive defense to shield IPs from reverse engineering （RE） based attacks. Integrated circuit （IC） camouflaging technique fills this gap by replacing some conventional logic gates in tile IPs with specially designed logic cells （called camouflaged gates） without changing the functions of tile IPs. The camouflaged gates can perform different logic functions while maintaining an identical look to RE attackers, thus preventing them from obtaining the layout information of the IP directly from RE tools. Since it was first proposed in 2012, circuit camouflaging has become one of the hottest research topics in hardware security focusing on two fundamental problems. How to choose the types of camouflaged gates and decide where to insert them in order to simultaneously minimize the performance overhead and optimize the RE complexity？ How can an attacker de-camouflage a camouflaged circuit and complete the RE attack？ In this article, we review the evolution of circuit camouflaging through this spear and shield race. First, we introduce the design methods of four different kinds of camouflaged ceils based on true/dummy contacts, static random access memory （SRAM）, doping, and emerging devices, respectively. Then we elaborate four representative de-camouflaging attacks： brute force attack, IC testing based attack, satisfiability-based （SAT-based） attack, and the circuit partition based attack, and the corresponding countermeasures： clique-based camouflaging, CamoPerturb, AND-tree camouflaging, and equivalent class based camouflaging, respectively. We argue that the current research efforts should be on reducing overhead introduced by circuit camouflaging and defeating decamouflaging attacks. We point out that exploring features of emerging devices could be a promising direction. Finally, as a complement to circuit camouflaging, we conclude with a brief review of other state-of-the-art IP protection techniques.

Design of high-speed and low-power finite-word-length PID controllers

ASIC or FPGA implementation of a finite word-length PID controller requires a double expertise： in control system and hardware design. In this paper, we only focus on the hardware side of the problem. We show how to design configurable fixed-point PIDs to satisfy applications requiring minimal power consumption, or high control-rate, or both together. As multiply operation is the engine of PID, we experienced three algorithms： Booth, modified Booth, and a new recursive multi-bit multiplication algorithm. This later enables the construction of finely grained PID structures with bit-level and unit-time precision. Such a feature permits to tailor the PID to the desired performance and power budget. All PIDs are implemented at register-transfer4evel （RTL） level as technology-independent reusable IP-cores. They are reconfigurable according to two compilemtime constants： set-point word-length and latency. To make PID design easily reproducible, all necessary implementation details are provided and discussed.