This paper presents a low power design for a 384 x 288 infrared （IR） readout integrated circuit （ROIC）. For the character of IR detector （ ro ≈ 100kΩ, Iint ≈ 100nA）, a novel pixel structure called quad-share ...This paper presents a low power design for a 384 x 288 infrared （IR） readout integrated circuit （ROIC）. For the character of IR detector （ ro ≈ 100kΩ, Iint ≈ 100nA）, a novel pixel structure called quad-share buffered direct injection （QSBDI） is proposed and realized. In QSBDI,four neighbor pixels share one buffered amplifier,which creates high injection efficiency, a stable bias, good FPN performance, and low power usage. This ROIC also supports two integration modes （integration then readout and integration while readout）, two selectable gains, and four window readout modes. A test 128 × 128 ROIC is designed,fabricated,and tested. The test results show that the ROIC has good linearity. The peak to peak variance of the sub array is about 10mV. The power of pixel stage is only lmW,and the total power dissipation is 37mW at a working frequency of 4MHz.展开更多
在航天遥感领域,波长在10μm以上的长波探测器仍以Hg Cd Te光导型探测器为主,在红外探测成像方面发挥着重要作用。非均匀性是目前长波光导探测器突出的问题之一,设计了一种数模混合的非均匀性校正的长波光导探测器读出电路。该电路不仅...在航天遥感领域,波长在10μm以上的长波探测器仍以Hg Cd Te光导型探测器为主,在红外探测成像方面发挥着重要作用。非均匀性是目前长波光导探测器突出的问题之一,设计了一种数模混合的非均匀性校正的长波光导探测器读出电路。该电路不仅可以有效地解决线列长波光导探测器电阻非均匀性问题,还可以增大ROIC输出信号的动态范围,几乎不增加读出电路功耗。经过仿真测试表明:非均匀性问题有了明显的改善,能够使其非均匀性降为0.5%以内,在常温和低温下都能正常工作。该校正电路不仅能解决当前工程中的关键问题,还对今后高性能大面阵长波光导探测器读出电路的设计具有重要的指导意义。展开更多
Current mirror integration（CMI） read out integrated circuit（ROIC） topology provides a low input impedance to photo-detectors and provides large injection efficiency, large charge handling capacity and snapshot mod...Current mirror integration（CMI） read out integrated circuit（ROIC） topology provides a low input impedance to photo-detectors and provides large injection efficiency, large charge handling capacity and snapshot mode operation without in-pixel opamps. The ROIC described in this paper has been implemented with a modified current mirror circuit, with matched PMOS pairs for detector input stage and its biasing. The readout circuit has been designed for 30×30μm^2 pixel size, 4×4 array size, variable frame rate, 5 Me charga pixel per second（Mpps）.Experimental performance of the test chip has achieved 15 Me charge handling capacity, a high dynamic range of83 dB, 99.8% linearity and 99.96% injection efficiency. The ROIC design has been fabricated in 3.3 V 1P6 MUMC180 nm CMOS process and tested up to 5 MHz pixel rate at room and at cryogenic temperature.展开更多
文摘This paper presents a low power design for a 384 x 288 infrared （IR） readout integrated circuit （ROIC）. For the character of IR detector （ ro ≈ 100kΩ, Iint ≈ 100nA）, a novel pixel structure called quad-share buffered direct injection （QSBDI） is proposed and realized. In QSBDI,four neighbor pixels share one buffered amplifier,which creates high injection efficiency, a stable bias, good FPN performance, and low power usage. This ROIC also supports two integration modes （integration then readout and integration while readout）, two selectable gains, and four window readout modes. A test 128 × 128 ROIC is designed,fabricated,and tested. The test results show that the ROIC has good linearity. The peak to peak variance of the sub array is about 10mV. The power of pixel stage is only lmW,and the total power dissipation is 37mW at a working frequency of 4MHz.
文摘在航天遥感领域,波长在10μm以上的长波探测器仍以Hg Cd Te光导型探测器为主,在红外探测成像方面发挥着重要作用。非均匀性是目前长波光导探测器突出的问题之一,设计了一种数模混合的非均匀性校正的长波光导探测器读出电路。该电路不仅可以有效地解决线列长波光导探测器电阻非均匀性问题,还可以增大ROIC输出信号的动态范围,几乎不增加读出电路功耗。经过仿真测试表明:非均匀性问题有了明显的改善,能够使其非均匀性降为0.5%以内,在常温和低温下都能正常工作。该校正电路不仅能解决当前工程中的关键问题,还对今后高性能大面阵长波光导探测器读出电路的设计具有重要的指导意义。
基金the support extended by Shri Tapan Mishra, Director, Space Applications Centre, Ahmedabad, IndiaSensor Development Area, Space Applications Centre, Ahmedabad, India for their support
文摘Current mirror integration（CMI） read out integrated circuit（ROIC） topology provides a low input impedance to photo-detectors and provides large injection efficiency, large charge handling capacity and snapshot mode operation without in-pixel opamps. The ROIC described in this paper has been implemented with a modified current mirror circuit, with matched PMOS pairs for detector input stage and its biasing. The readout circuit has been designed for 30×30μm^2 pixel size, 4×4 array size, variable frame rate, 5 Me charga pixel per second（Mpps）.Experimental performance of the test chip has achieved 15 Me charge handling capacity, a high dynamic range of83 dB, 99.8% linearity and 99.96% injection efficiency. The ROIC design has been fabricated in 3.3 V 1P6 MUMC180 nm CMOS process and tested up to 5 MHz pixel rate at room and at cryogenic temperature.
