Comparison of displacement damage effects on the dark signal in CMOS image sensors induced by CSNS back-n and XAPR neutrons

This study investigates the effects of displacement damage on the dark signal of a pinned photodiode CMOS image sensor(CIS)following irradiation with back-streaming white neutrons from white neutron sources at the China spallation neutron source(CSNS)and Xi'an pulsed reactor(XAPR).The mean dark signal,dark signal non-uniformity(DSNU),dark signal distribution,and hot pixels of the CIS were compared between the CSNS back-n and XAPR neutron irradiations.The nonionizing energy loss and energy distribution of primary knock-on atoms in silicon,induced by neutrons,were calculated using the open-source package Geant4.An analysis combining experimental and simulation results showed a noticeable proportionality between the increase in the mean dark signal and the displacement damage dose(DDD).Additionally,neutron energies influence DSNU,dark signal distribution,and hot pixels.High neutron energies at the same DDD level may lead to pronounced dark signal non-uniformity and elevated hot pixel values.

A Low-Power-Consumption 9bit 10MS/s Pipeline ADC for CMOS Image Sensors

A low-power-consumption 9bit 10MS/s pipeline ADC,used in a CMOS image sensor,is proposed. In the design, the decrease of power consumption is achieved by applying low-power-consumption and large-output-swing amplifiers with gain boost structure, and biasing all the cells with the same voltage bias source, which requires careful layout design and large capacitors. In addition,capacitor array DAC is also applied to reduce power consumption,and low threshold voltage MOS transistors are used to achieve a large signal processing range. The ADC was implemented in a 0.18μm 4M-1 P CMOS process,and the experimental results indicate that it consumes only 7mW, which is much less than general pipeline ADCs. The ADC was used in a 300000 pixels CMOS image sensor.

Localized Model and Arithmetic System Based on Two Image Sensors Under Complex Circumstance

Two image sensors simulate directly the way of disposing images with the human＇s two eyes, so it has important value to apply in many domains, such as object identification, small unmaned aerial vehicle （UAV）, workpiece localization, robot navigation and so on. The object localization based on two image sensots is studied in this paper. It concentrates on how to apply two charge coupled device （CCD） image sensors to object localization of sphere in complex environments. At first a space model of the two image sensors is set up, then Hough transformation is adopted to get localizated model and arithmetic system. An experiment platform is built in order to prove the correctness and feasibility of that localization algorithm.

Dark output characteristic of γ-ray irradiated CMOS digital image sensors

The quality of dark output images from the CMOS (complementarymetal oxide semiconductor) black and white (B & W) digital imagesensors captured before and after γ-ray irradiation was studied. Thecharacteristic parameters of the dark output images captured atdifferent radiation dose, e.g. average brightness and itsnon-uniformity of dark out- put images, were analyzed by our testsoftware. The primary explanation for the change of the parameterswith the radi- ation dose was given.

Modeling the photon counting and photoelectron counting characteristics of quanta image sensors

A signal chain model of single-bit and multi-bit quanta image sensors(QISs)is established.Based on the proposed model,the photoresponse characteristics and signal error rates of QISs are investigated,and the effects of bit depth,quantum efficiency,dark current,and read noise on them are analyzed.When the signal error rates towards photons and photoelectrons counting are lower than 0.01,the high accuracy photon and photoelectron counting exposure ranges are determined.Furthermore,an optimization method of integration time to ensure that the QIS works in these high accuracy exposure ranges is presented.The trade-offs between pixel area,the mean value of incident photons,and integration time under different illuminance level are analyzed.For the 3-bit QIS with 0.16 e-/s dark current and 0.21 e-r.m.s.read noise,when the illuminance level and pixel area are 1 lux and 1.21μm^(2),or 10000 lux and 0.21μm^(2),the recommended integration time is 8.8 to 30 ms,or 10 to21.3μs,respectively.The proposed method can guide the design and operation of single-bit and multi-bit QISs.

Difference in electron-and gamma-irradiation effects on output characteristic of color CMOS digital image sensors

Changes of the average brightness and non-uniformity of dark output images,and quality of pictures captured under natural lighting for the color CMOS digital image sensorsirradiated at different electron doses have been studied in comparison to those from theγ-irradiated sensors. For the electron-irradiated sensors, the non-uniformity increases obviouslyand a small bright region on the dark image appears at the dose of 0.4 kGy. The average brightnessincreases at 0.4 kGy, increases sharply at 0.5 kGy. The picture is very blurry only at 0.6 kGy,showing the sensor undergoes severe performance degradation. Electron radiation damage is much moresevere than γ radiation damage for the CMOS image sensors. A possible explanation is presented inthis paper.

High Speed Column-Parallel CDS/ADC Circuit with Nonlinearity Compensation for CMOS Image Sensors

A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper.The correlated double sampling (CDS) and analog-to-digital converter (ADC) functions are integrated in a threephase column-parallel circuit based on two floating gate inverters and switched-capacitor network.The conversion rate of traditional single-slope ADC is speeded up by dividing quantization to coarse step and fine step.A storage capacitor is used to store the result of coarse step and locate the section of ramp signal of fine step,which can reduce the clock step from 2 n to 2 (n/2+1).The floating gate inverters are implemented to reduce the power consumption.Its induced nonlinear offset is cancelled by introducing a compensation module to the input of inverter,which can equalize the coupling path in three phases of the proposed circuit.This circuit is designed and simulated for CMOS image sensor with 640×480 pixel array using Chartered 0.18μm process.Simulation results indicate that the resolution can reach 10-bit and the maximum frame rate can reach 200 frames/s with a main clock of 10MHz.The power consumption of this circuit is less than 36.5μW with a 3.3V power supply.The proposed CDS/ADC circuit is suitable for high resolution and high speed image sensors.

Time-dependent crosstalk effects for image sensors with different isolation structures

Photo-generated carriers may diffuse into the adjacent cells to form the electrical crosstalk, which is especially no- ticeable after the pixel cell size has been scaled down. The electrical crosstalk strongly depends on the structure and electrical properties of the photosensitive areas. In this work, time-dependent crosstalk effects considering different isola- tion structures are investigated. According to the different depths of photo-diode （PD） and isolation structure, the transport of photo-generated carriers is analyzed with different regions in the pixel cell. The evaluation of crosstalk is influenced by exposure time. Crosstalk can be suppressed by reducing the exposure time. However, the sensitivity and dynamic range of the image sensor need to be considered as well.

In-Pixel Charge Addition Scheme Applied in Time-Delay Integration CMOS Image Sensors

An addition scheme applicable to time-delay integration (TDI) CMOS image sensor is proposed,which adds signals in the charge domain in the pixel array.A two-shared pixel structure adopting two-stage charge transfer is introduced,together with the rolling shutter with an undersampling readout timing.Compared with the conventional TDI addition methods,the proposed scheme can reduce the addition operations by half in the pixel array,which decreases the power consumption of addition circuits outside the pixel array.The timing arrangement and pixel structure are analyzed in detail.The simulation results show that the proposed pixel structure can achieve the charge addition with negligible nonlinearity,therefore the power consumption of the periphery addition circuits can be reduced by half theoretically.

Review of bio-inspired image sensors for efficient machine vision

With the rapid development of sensor networks,machine vision faces the problem of storing and computing massive data.The human visual system has a very efficient information sense and computation ability,which has enlightening significance for solving the above problems in machine vision.This review aims to comprehensively summarize the latest advances in bio-inspired image sensors that can be used to improve machine-vision processing efficiency.After briefly introducing the research background,the relevant mechanisms of visual information processing in human visual systems are briefly discussed,including layerby-layer processing,sparse coding,and neural adaptation.Subsequently,the cases and performance of image sensors corresponding to various bio-inspired mechanisms are introduced.Finally,the challenges and perspectives of implementing bio-inspired image sensors for efficient machine vision are discussed.

Process techniques of charge transfer time reduction for high speed CMOS image sensors

This paper proposes pixel process techniques to reduce the charge transfer time in high speed CMOS image sensors. These techniques increase the lateral conductivity of the photo-generated carriers in a pinned photodiode （PPD） and the voltage difference between the PPD and the floating diffusion （FD） node by controlling and optimizing the N doping concentration in the PPD and the threshold voltage of the reset transistor, respectively. The techniques shorten the charge transfer time from the PPD diode to the FD node effectively. The proposed process techniques do not need extra masks and do not cause harm to the fill factor. A sub array of 32 x 64 pixels was designed and implemented in the 0.18 #m CIS process with five implantation conditions splitting the N region in the PPD. The simulation and measured results demonstrate that the charge transfer time can be decreased by using the proposed techniques. Comparing the charge transfer time of the pixel with the different implantation conditions of the N region, the charge transfer time of 0.32 μs is achieved and 31% of image lag was reduced by using the proposed process techniques.

Image Restoration After Pixel Binning in Image Sensors

A method was developed to restore degraded images to some extent after the pixel binning pro- cess in image sensors to improve the resolution. A pixel binning model was used to approximate the original un-binned image. Then, the least squares error criterion was used as a constraint to reconstruct the re- stored pixel values from the binning model. The technique achieves about a one-decibel increase in the peak signal-to-noise ratio compared with the original estimated image. The technique has good detail pre- servation performance as well as low computation load. Thus, this restoration technique provides valuable improvements in practical, real time image processing.

Measurement of charge transfer potential barrier in pinned photodiode CMOS image sensors

The charge transfer potential barrier （CTPB） formed beneath the transfer gate causes a noticeable image lag issue in pinned photodiode （PPD） CMOS image sensors （CIS）, and is difficult to measure straightforwardly since it is embedded inside the device. From an understanding of the CTPB formation mechanism, we report on an alternative method to feasibly measure the CTPB height by performing a linear extrapolation coupled with a horizontal left-shift on the sensor photoresponse curve under the steady-state illumination. The theoretical study was pertbrmed in detail on the principle of the proposed method. Application of the measurements oil a prototype PPD-CIS chip with an array of 160 ×160 pixels is demonstrated. Such a method intends to shine new light oil the guidance for the lag-free and high-speed sensors optimization based on PPD devices.

A linear stepping PGA used in CMOS image sensors

A low power linear stepping digital programming gain amplifier （PGA） is designed for CMOS image sensors. The PGA consists of three stages with gain range from one to nine, The gain is divided into four regions and each range has 128 linear steps. Power consumption of the PGA is saved by good tradeoff between variation of amplifier feedback coefficient, pipeline stages and gain regions. With thermometer-binary mixed coding and linear pipeline gain stepping, the load capacitance keeps constant when the gain of one stage is changed. The PGA is designed in the SMIC 0.18 μm process. Simulation results show that the power consumption is 3.2 mW with 10 bit resolution and 10 MSPS sampling rate. The PGA has been embedded in a 0.3 megapixel CMOS image sensors and fabricated successfully.

Highly aligned organic microwire crystal arrays for high-performance polarization-sensitive photodetectors and image sensors

Organic semiconductors with excellent optoelectronic properties are important building blocks for highperformance organic devices.Patterning organic crystals with high precision and accurately positioning them at the target position are major challenges for integrated devices.However,uncontrollable dewetting of the conventional solution method leads to as-prepared micro-nanocrystals with high defect-state density,low crystalline quality,and disordered distribution,which impair the uniformity of the device performance and limit integration.By regulating the solution position with a template and guiding the solution flow direction under gravity,aligned organic microwire arrays and polygonal patterns were fabricated.The polarization-sensitive photodetector exhibited responsivity up to 1234 A W^(-1),linear dynamic range of 148 dB,I_(photo)/I_(dark)of 10^(4),response time as low as 1.1 ms,and dichroic ratio up to 2.1.Given the homogeneity of microwire arrays,the device-to-device variation was reduced to 3.58%,resulting in high-quality imaging.This study provides new insights into organic micro/nanocrystal patterning and device integration.

A 10-bit column-parallel cyclic ADC for high-speed CMOS image sensors

This paper presents a high-speed column-parallel cyclic analog-to-digital converter（ADC） for a CMOS image sensor.A correlated double sampling（CDS） circuit is integrated in the ADC,which avoids a stand-alone CDS circuit block.An offset cancellation technique is also introduced,which reduces the column fixed-pattern noise（FPN） effectively.One single channel ADC with an area less than 0.02 mm^2 was implemented in a 0.13μm CMOS image sensor process.The resolution of the proposed ADC is 10-bit,and the conversion rate is 1.6 MS/s. The measured differential nonlinearity and integral nonlinearity are 0.89 LSB and 6.2 LSB together with CDS, respectively.The power consumption from 3.3 V supply is only 0.66 mW.An array of 48 10-bit column-parallel cyclic ADCs was integrated into an array of CMOS image sensor pixels.The measured results indicated that the ADC circuit is suitable for high-speed CMOS image sensors.

Reset noise reduction through column-level feedback reset in CMOS image sensors

A low reset noise CMOS image sensor （CIS） based on column-level feedback reset is proposed. A feedback loop was formed through an amplifier and a switch. A prototype CMOS image sensor was developed with a 0.18μm CIS process. Through matching the noise bandwidth and the bandwidth of the amplifier, with the falling time period of the reset impulse 6μs, experimental results show the reset noise level can experience up to 25 dB reduction. The proposed CMOS image sensor meets the demand of applications in high speed security surveillance systems, especially in low illumination.

High-stage analog accumulator for TDI CMOS image sensors

The impact of the parasitic phenomenon on the performance of the analog accumulator in TDI CMOS image sensor is analyzed and resolved. A 128-stage optimized accumulator based on 0.18-μm one-poly four-metal 3.3 V CMOS technology is designed and simulated. A charge injection effect from the top plate sampling is em- ployed to compensate the un-eliminated parasitics based on the accumulator with a decoupling switch, and then a calibration circuit is designed to restrain the mismatch and Process, Voltage and Temperature （PVT） variations. The post layout simulation indicates that the improved SNR of the accumulator upgrades from 17.835 to 21.067 dB, while an ideal value is 21.072 dB. In addition, the linearity of the accumulator is 99.62%. The simulation results of two extreme cases and Monte Carlo show that the mismatch and PVT variations are restrained by the calibration circuit. Furthermore, it is promising to design a higher stage accumulator based on the proposed structure.

Incomplete charge transfer in CMOS image sensor caused by Si/SiO_(2)interface states in the TG channel

CMOS image sensors produced by the existing CMOS manufacturing process usually have difficulty achieving complete charge transfer owing to the introduction of potential barriers or Si/SiO_(2)interface state traps in the charge transfer path,which reduces the charge transfer efficiency and image quality.Until now,scholars have only considered mechanisms that limit charge transfer from the perspectives of potential barriers and spill back effect under high illumination condition.However,the existing models have thus far ignored the charge transfer limitation due to Si/SiO_(2)interface state traps in the transfer gate channel,particularly under low illumination.Therefore,this paper proposes,for the first time,an analytical model for quantifying the incomplete charge transfer caused by Si/SiO_(2)interface state traps in the transfer gate channel under low illumination.This model can predict the variation rules of the number of untransferred charges and charge transfer efficiency when the trap energy level follows Gaussian distribution,exponential distribution and measured distribution.The model was verified with technology computer-aided design simulations,and the results showed that the simulation results exhibit the consistency with the proposed model.

Neuromorphic vision sensors: Principle, progress and perspectives

Conventional frame-based image sensors suffer greatly from high energy consumption and latency.Mimicking neurobiological structures and functionalities of the retina provides a promising way to build a neuromorphic vision sensor with highly efficient image processing.In this review article,we will start with a brief introduction to explain the working mechanism and the challenges of conventional frame-based image sensors,and introduce the structure and functions of biological retina.In the main section,we will overview recent developments in neuromorphic vision sensors,including the silicon retina based on conventional Si CMOS digital technologies,and the neuromorphic vision sensors with the implementation of emerging devices.Finally,we will provide a brief outline of the prospects and outlook for the development of this field.