Localized Model and Arithmetic System Based on Two Image Sensors Under Complex Circumstance

Two image sensors simulate directly the way of disposing images with the human＇s two eyes, so it has important value to apply in many domains, such as object identification, small unmaned aerial vehicle （UAV）, workpiece localization, robot navigation and so on. The object localization based on two image sensots is studied in this paper. It concentrates on how to apply two charge coupled device （CCD） image sensors to object localization of sphere in complex environments. At first a space model of the two image sensors is set up, then Hough transformation is adopted to get localizated model and arithmetic system. An experiment platform is built in order to prove the correctness and feasibility of that localization algorithm.

Dark output characteristic of γ-ray irradiated CMOS digital image sensors

The quality of dark output images from the CMOS (complementarymetal oxide semiconductor) black and white (B & W) digital imagesensors captured before and after γ-ray irradiation was studied. Thecharacteristic parameters of the dark output images captured atdifferent radiation dose, e.g. average brightness and itsnon-uniformity of dark out- put images, were analyzed by our testsoftware. The primary explanation for the change of the parameterswith the radi- ation dose was given.

Modeling the photon counting and photoelectron counting characteristics of quanta image sensors

A signal chain model of single-bit and multi-bit quanta image sensors(QISs)is established.Based on the proposed model,the photoresponse characteristics and signal error rates of QISs are investigated,and the effects of bit depth,quantum efficiency,dark current,and read noise on them are analyzed.When the signal error rates towards photons and photoelectrons counting are lower than 0.01,the high accuracy photon and photoelectron counting exposure ranges are determined.Furthermore,an optimization method of integration time to ensure that the QIS works in these high accuracy exposure ranges is presented.The trade-offs between pixel area,the mean value of incident photons,and integration time under different illuminance level are analyzed.For the 3-bit QIS with 0.16 e-/s dark current and 0.21 e-r.m.s.read noise,when the illuminance level and pixel area are 1 lux and 1.21μm^(2),or 10000 lux and 0.21μm^(2),the recommended integration time is 8.8 to 30 ms,or 10 to21.3μs,respectively.The proposed method can guide the design and operation of single-bit and multi-bit QISs.

Difference in electron-and gamma-irradiation effects on output characteristic of color CMOS digital image sensors

Changes of the average brightness and non-uniformity of dark output images,and quality of pictures captured under natural lighting for the color CMOS digital image sensorsirradiated at different electron doses have been studied in comparison to those from theγ-irradiated sensors. For the electron-irradiated sensors, the non-uniformity increases obviouslyand a small bright region on the dark image appears at the dose of 0.4 kGy. The average brightnessincreases at 0.4 kGy, increases sharply at 0.5 kGy. The picture is very blurry only at 0.6 kGy,showing the sensor undergoes severe performance degradation. Electron radiation damage is much moresevere than γ radiation damage for the CMOS image sensors. A possible explanation is presented inthis paper.

Time-dependent crosstalk effects for image sensors with different isolation structures

Photo-generated carriers may diffuse into the adjacent cells to form the electrical crosstalk, which is especially no- ticeable after the pixel cell size has been scaled down. The electrical crosstalk strongly depends on the structure and electrical properties of the photosensitive areas. In this work, time-dependent crosstalk effects considering different isola- tion structures are investigated. According to the different depths of photo-diode （PD） and isolation structure, the transport of photo-generated carriers is analyzed with different regions in the pixel cell. The evaluation of crosstalk is influenced by exposure time. Crosstalk can be suppressed by reducing the exposure time. However, the sensitivity and dynamic range of the image sensor need to be considered as well.

Process techniques of charge transfer time reduction for high speed CMOS image sensors

This paper proposes pixel process techniques to reduce the charge transfer time in high speed CMOS image sensors. These techniques increase the lateral conductivity of the photo-generated carriers in a pinned photodiode （PPD） and the voltage difference between the PPD and the floating diffusion （FD） node by controlling and optimizing the N doping concentration in the PPD and the threshold voltage of the reset transistor, respectively. The techniques shorten the charge transfer time from the PPD diode to the FD node effectively. The proposed process techniques do not need extra masks and do not cause harm to the fill factor. A sub array of 32 x 64 pixels was designed and implemented in the 0.18 #m CIS process with five implantation conditions splitting the N region in the PPD. The simulation and measured results demonstrate that the charge transfer time can be decreased by using the proposed techniques. Comparing the charge transfer time of the pixel with the different implantation conditions of the N region, the charge transfer time of 0.32 μs is achieved and 31% of image lag was reduced by using the proposed process techniques.

Image Restoration After Pixel Binning in Image Sensors

A method was developed to restore degraded images to some extent after the pixel binning pro- cess in image sensors to improve the resolution. A pixel binning model was used to approximate the original un-binned image. Then, the least squares error criterion was used as a constraint to reconstruct the re- stored pixel values from the binning model. The technique achieves about a one-decibel increase in the peak signal-to-noise ratio compared with the original estimated image. The technique has good detail pre- servation performance as well as low computation load. Thus, this restoration technique provides valuable improvements in practical, real time image processing.

Measurement of charge transfer potential barrier in pinned photodiode CMOS image sensors

The charge transfer potential barrier （CTPB） formed beneath the transfer gate causes a noticeable image lag issue in pinned photodiode （PPD） CMOS image sensors （CIS）, and is difficult to measure straightforwardly since it is embedded inside the device. From an understanding of the CTPB formation mechanism, we report on an alternative method to feasibly measure the CTPB height by performing a linear extrapolation coupled with a horizontal left-shift on the sensor photoresponse curve under the steady-state illumination. The theoretical study was pertbrmed in detail on the principle of the proposed method. Application of the measurements oil a prototype PPD-CIS chip with an array of 160 ×160 pixels is demonstrated. Such a method intends to shine new light oil the guidance for the lag-free and high-speed sensors optimization based on PPD devices.

A linear stepping PGA used in CMOS image sensors

A low power linear stepping digital programming gain amplifier （PGA） is designed for CMOS image sensors. The PGA consists of three stages with gain range from one to nine, The gain is divided into four regions and each range has 128 linear steps. Power consumption of the PGA is saved by good tradeoff between variation of amplifier feedback coefficient, pipeline stages and gain regions. With thermometer-binary mixed coding and linear pipeline gain stepping, the load capacitance keeps constant when the gain of one stage is changed. The PGA is designed in the SMIC 0.18 μm process. Simulation results show that the power consumption is 3.2 mW with 10 bit resolution and 10 MSPS sampling rate. The PGA has been embedded in a 0.3 megapixel CMOS image sensors and fabricated successfully.

A 10-bit column-parallel cyclic ADC for high-speed CMOS image sensors

This paper presents a high-speed column-parallel cyclic analog-to-digital converter（ADC） for a CMOS image sensor.A correlated double sampling（CDS） circuit is integrated in the ADC,which avoids a stand-alone CDS circuit block.An offset cancellation technique is also introduced,which reduces the column fixed-pattern noise（FPN） effectively.One single channel ADC with an area less than 0.02 mm^2 was implemented in a 0.13μm CMOS image sensor process.The resolution of the proposed ADC is 10-bit,and the conversion rate is 1.6 MS/s. The measured differential nonlinearity and integral nonlinearity are 0.89 LSB and 6.2 LSB together with CDS, respectively.The power consumption from 3.3 V supply is only 0.66 mW.An array of 48 10-bit column-parallel cyclic ADCs was integrated into an array of CMOS image sensor pixels.The measured results indicated that the ADC circuit is suitable for high-speed CMOS image sensors.

Reset noise reduction through column-level feedback reset in CMOS image sensors

A low reset noise CMOS image sensor （CIS） based on column-level feedback reset is proposed. A feedback loop was formed through an amplifier and a switch. A prototype CMOS image sensor was developed with a 0.18μm CIS process. Through matching the noise bandwidth and the bandwidth of the amplifier, with the falling time period of the reset impulse 6μs, experimental results show the reset noise level can experience up to 25 dB reduction. The proposed CMOS image sensor meets the demand of applications in high speed security surveillance systems, especially in low illumination.

High-stage analog accumulator for TDI CMOS image sensors

The impact of the parasitic phenomenon on the performance of the analog accumulator in TDI CMOS image sensor is analyzed and resolved. A 128-stage optimized accumulator based on 0.18-μm one-poly four-metal 3.3 V CMOS technology is designed and simulated. A charge injection effect from the top plate sampling is em- ployed to compensate the un-eliminated parasitics based on the accumulator with a decoupling switch, and then a calibration circuit is designed to restrain the mismatch and Process, Voltage and Temperature （PVT） variations. The post layout simulation indicates that the improved SNR of the accumulator upgrades from 17.835 to 21.067 dB, while an ideal value is 21.072 dB. In addition, the linearity of the accumulator is 99.62%. The simulation results of two extreme cases and Monte Carlo show that the mismatch and PVT variations are restrained by the calibration circuit. Furthermore, it is promising to design a higher stage accumulator based on the proposed structure.

Incomplete charge transfer in CMOS image sensor caused by Si/SiO_(2)interface states in the TG channel

CMOS image sensors produced by the existing CMOS manufacturing process usually have difficulty achieving complete charge transfer owing to the introduction of potential barriers or Si/SiO_(2)interface state traps in the charge transfer path,which reduces the charge transfer efficiency and image quality.Until now,scholars have only considered mechanisms that limit charge transfer from the perspectives of potential barriers and spill back effect under high illumination condition.However,the existing models have thus far ignored the charge transfer limitation due to Si/SiO_(2)interface state traps in the transfer gate channel,particularly under low illumination.Therefore,this paper proposes,for the first time,an analytical model for quantifying the incomplete charge transfer caused by Si/SiO_(2)interface state traps in the transfer gate channel under low illumination.This model can predict the variation rules of the number of untransferred charges and charge transfer efficiency when the trap energy level follows Gaussian distribution,exponential distribution and measured distribution.The model was verified with technology computer-aided design simulations,and the results showed that the simulation results exhibit the consistency with the proposed model.

Neuromorphic vision sensors: Principle, progress and perspectives

Conventional frame-based image sensors suffer greatly from high energy consumption and latency.Mimicking neurobiological structures and functionalities of the retina provides a promising way to build a neuromorphic vision sensor with highly efficient image processing.In this review article,we will start with a brief introduction to explain the working mechanism and the challenges of conventional frame-based image sensors,and introduce the structure and functions of biological retina.In the main section,we will overview recent developments in neuromorphic vision sensors,including the silicon retina based on conventional Si CMOS digital technologies,and the neuromorphic vision sensors with the implementation of emerging devices.Finally,we will provide a brief outline of the prospects and outlook for the development of this field.

Weld pool image sensor for pulsed MIG welding

Visual image sensor is developed to detect the weld pool images in pulsed MIG welding. An exposure controller, which is composed of the modules of the voltage transforming, the exposure parameters presetting, the complex programmable logic device （CPLD） based logic controlling, exposure signal processing, the arc state detecting, the mechanical iris driving and so on, is designed at first. Then, a visual image sensor consists of an ordinary CCD camera, optical system and exposure controller is established. The exposure synchronic control logic is described with very-high-speed integrated circuit hardware description language （VHDL） and programmed with CPLD , to detect weld pool images at the stage of base current in pulsed MIG welding. Finally, both bead on plate welding and V groove filled welding are carried out, clear and consistent weld pool images are acquired.

A nano-metallic-particles-based CMOS image sensor for DNA detection

In this paper we report on a study of the CMOS image sensor detection of DNA based on self-assembled nano- metallic particles, which are selectively deposited on the surface of the passive image sensor. The nano-metallic particles effectively block the optical radiation in the visible spectrum of ordinary light source. When such a technical method is applied to DNA detection, the requirement for a special UV light source in the most popular fluorescence is eliminated. The DNA detection methodology is tested on a CMOS sensor chip fabricated using a standard 0.5 gm CMOS process. It is demonstrated that the approach is highly selective to detecting even a signal-base mismatched DNA target with an extremely-low-concentration DNA sample down to 10 pM under an ordinary light source.

Modeling random telegraph signal noise in CMOS image sensor under low light based on binomial distribution

The random telegraph signal noise in the pixel source follower MOSFET is the principle component of the noise in the CMOS image sensor under low light. In this paper, the physical and statistical model of the random telegraph signal noise in the pixel source follower based on the binomial distribution is set up. The number of electrons captured or released by the oxide traps in the unit time is described as the random variables which obey the binomial distribution. As a result,the output states and the corresponding probabilities of the first and the second samples of the correlated double sampling circuit are acquired. The standard deviation of the output states after the correlated double sampling circuit can be obtained accordingly. In the simulation section, one hundred thousand samples of the source follower MOSFET have been simulated,and the simulation results show that the proposed model has the similar statistical characteristics with the existing models under the effect of the channel length and the density of the oxide trap. Moreover, the noise histogram of the proposed model has been evaluated at different environmental temperatures.

Column readout circuit with improved offset mismatch and charge sharing for CMOS image sensor

High linearity and low noise column readout chain are two key factors in CMOS image sensor.However,offset mismatch and charge sharing always exist in the conventional column wise readout implementation,even adopting the technology of correlated double sample.A simple column readout circuit with improved offset mismatch and charge sharing for CMOS image sensor is proposed in this paper.Based on the bottom plate sampling and fixed common level method,this novel design can avoid the offset nonuniformity between the two buffers.Also,the single buffer and switched capacitor technique can effectively suppress the charge sharing caused by the varied operating point.The proposed approach is experimentally verified in a 1024×1024 prototype chip designed and fabricated in 55 nm low power CMOS process.The measurement results show that the linear range is extended by 20%,the readout noise of bright and dark fields is reduced by 40%and 30%respectively,and the improved photo response nonuniformity is up to 1.16%.Finally,a raw sample image taken by the prototype sensor shows the excellent practical performance.

A quantum efficiency analytical model for complementary metal–oxide–semiconductor image pixels with a pinned photodiode structure

A quantum efficiency analytical model for complementary metal–oxide–semiconductor（CMOS） image pixels with a pinned photodiode structure is developed. The proposed model takes account of the non-uniform doping distribution in the N-type region due to the impurity compensation formed by the actual fabricating process. The characteristics of two boundary PN junctions located in the N-type region for the particular spectral response of a pinned photodiode, are quantitatively analyzed. By solving the minority carrier steady-state diffusion equations and the barrier region photocurrent density equations successively, the analytical relationship between the quantum efficiency and the corresponding parameters such as incident wavelength, N-type width, peak doping concentration, and impurity density gradient of the N-type region is established. The validity of the model is verified by the measurement results with a test chip of 160×160 pixels array,which provides the accurate process with a theoretical guidance for quantum efficiency design in pinned photodiode pixels.

A low-power high-quality CMOS image sensor using 1.5 V 4T pinned photodiode and dual-CDS column-parallel single-slope ADC

This paper presents a low-power high-quality CMOS image sensor(CIS)using 1.5 V 4T pinned photodiode(4T-PPD)and dual correlated double sampling(dual-CDS)column-parallel single-slope ADC.A five-finger shaped pixel layer is proposed to solve image lag caused by low-voltage 4T-PPD.Dual-CDS is used to reduce random noise and the nonuniformity between columns.Dual-mode counting method is proposed to improve circuit robustness.A prototype sensor was fabricated using a 0.11μm CMOS process.Measurement results show that the lag of the five-finger shaped pixel is reduced by 80%compared with the conventional rectangular pixel,the chip power consumption is only 36 mW,the dynamic range is 67.3 dB,the random noise is only 1.55 e^(-)_(rms),and the figure-of-merit is only 1.98 e^(-)·nJ,thus realizing low-power and high-quality imaging.