CMOS Direct-Injection Divide-by-3 Injection-Locked Frequency Dividers

This paper proposes CMOS LC-tank divide-by-3 injection locked frequency dividers(ILFDs)fabricated in 0.18μn and 90nm CMOS process and describes the circuit design,operation principle and measurement results of the ILFDs.The ILFDs use two injection series-MOSFETs across the LC resonator and a differential injection signal is applied to the gates of injection MOSFETs.The direct-injection divide-by-3 ILFDs are potential for radio-frequency application and can have wide locking range.

A 30GHz Wideband CMOS Injection-Locked Frequency Divider for 60GHz Transceiver

In this paper, a 30 GHz wide locking-range (26.2 GHz-35.7 GHz) direct injection-locked frequency divider (ILFD), which operating in the millimeter-wave (MMW) band, is presented. The locking range of the ILFD is extended by using differential injection topology. Besides, varactors are used in RLC resonant tank for extending the frequency tuning range. The post simulation results show that a wide locking-range of 9.5 GHz (30.7%) is achieved. When the VCO output frequency varies from 26.85 GHz to 34.42 GHz, the proposed ILFD can achieve divide-by-two correctly. Designed in 0.13 μm CMOS technology, the ILFD occupies a core area of 0.76 mm2 while drawing 7 mA of current from 2.5 V power supply.

A 31–45.5 GHz injection-locked frequency divider in 90-nm CMOS technology

We present a 31–45.5 GHz injection-locked frequency divider(ILFD) implemented in a standard 90-nm CMOS process. To reduce parasitic capacitance and increase the operating frequency, an NMOS-only cross-coupled pair is adopted to provide negative resistance. Acting as an adjustable resistor, an NMOS transistor with a tunable gate bias voltage is connected to the differential output terminals for locking range extension. Measurements show that the designed ILFD can be fully functional in a wide locking range and provides a good figure-of-merit. Under a 1 V tunable bias voltage, the self-resonant frequency of the divider is 19.11 GHz and the maximum locking range is 37.7% at 38.5 GHz with an input power of 0 d Bm. The power consumption is 2.88 m W under a supply voltage of 1.2 V. The size of the chip including the pads is 0.62 mm×0.42 mm.

Low-power wide-locking-range injection-locked frequency divider for OFDM UWB systems

This paper describes a divide-by-two injection-locked frequency divider （ILFD） for frequency synthesizers as used in multiband orthogonal frequency division multiplexing （OFDM） ultra-wideband （UWB） systems. By means of dual-injection technique and other conventional tuning techniques, such as DCCA and varactor tuning, the divider demonstrates a wide locking range while consuming much less power. The chip was fabricated in the Jazz 0.18μm RF CMOS process. The measurement results show that the divider achieves a locking range of 4.85 GHz （6.23 to 11.08 GHz） at an input power of 8 dBm. The core circuit without the test buffer consumes only 3.7 mA from a 1.8 V power supply and has a die area of 0.38×0.28 mm^2. The wide locking range combined with low power consumption makes the ILFD suitable for its application in UWB systems.

A Programmable 2.4GHz CMOS Multi-Modulus Frequency Divider

A programmable multi-modulus frequency divider is designed and implemented in a 0. 35μm CMOS process. The multi-modulus frequency divider is a single chip with two dividers in series,which are divided by 4 or 5 prescaler and by 128-255 multi-modulus frequency divider. In the circuit design, power and speed trade-offs are analyzed for the prescaler, and power optimization techniques are used according to the input frequency of each divider cell for the 128-255 multimodulus frequency divider. The chip is designed with ESD protected I/O PAD. The dividers chain can work as high as 2.4GHz with a single ended input signal and beyond 2.6GHz with differential input signals. The dual-modulus prescaler consumes 11mA of current while the 128-255 multi-modulus frequency divider consumes 17mA of current with a 3.3V power supply. The core area of the die without PAD is 0.65mm × 0.3mm. This programmable multi-modulus frequency divider can be used for 2.4GHz ISM band PLL-based frequency synthesizers. To our knowledge, this is the first reported multi-modulus frequency divider with this structure in China.

0.18μm CMOS programmable frequency divider design for DVB-T

The implementation of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for digital video broadcastingterrestrial （DVB-T） and other modem communication systems, is presented. By cooperating with a dual-modulus prescaler, this divider can realize an integer frequency division from 926 to 1 387. Besides the traditional standard cell design flow, such as logic synthesis, placement and routing, the interactions between front-end and back-end are also considered to optimize the design flow under deep submicron technology. By back-annotating the back-end information to front-end design, a custom wire-load model is created which is more practical compared with the default model. This divider has been fabricated in TSMC 0. 18μm CMOS technology using Artisan standard cell library. The chip area is 675 μm × 475 μm and the power consumption is about 2 mW under a 1.8 V power supply. Measurement results show that it works correctly and can realize a frequency division with high precision.

An 8.5GHz 1∶8 Frequency Divider in 0.35μm CMOS Technology

An 1∶8 frequency divider is designed and realized in a 0 35μm standard CMOS technology.The chip consists of three stages of 1∶2 divider cells,which are constructed with source couple logic (SCL) flip flops.By revising the traditional topology of SCL flip flop,a divider with better performances is got.The results of measurement show that the whole chip achieves the frequency division at more than 8 5GHz.Each 1∶2 divider consumes about 11mW from a 3 3V supply.The divider can be used in RF and optic fiber transceivers and other high speed systems.

Design of a Frequency Divider with Reduced Complexity Based on a Resonant Tunneling Diode

A novel edge-triggered D-flip-flop based on a resonant tunneling diode （RTD） is proposed and used to construct a binary frequency divider. The design is discussed in detail and the performance of the circuit is verified using SPICE. Relying on the nonlinear characteristics of RTD,we reduced the number of components used in our DFF circuit to only half of that required using conventional CMOS SCFL technology.

A Low Power,High Sensitivity SiGe HBT Static Frequency Divider up to 90 GHz for Millimeter-Wave Application

A layout and connection optimization for static frequency divider is presented. The layout optimization provides a new circle topology transistors placement and reasonable connection structure, which reduces the parasitic effectively and enables self-oscillation frequency enhancement. Besides, bandwidth enhancement techniques based on a center-tap capacitor in input balun design and inductive peaking in latch design are adopted to improve further high frequency performance with low power consumption. As a proof of concept, design of a divide-by-2 static frequency divider in 0.13 μm SiGe BiCMOS technology is reported. With single-ended input clock signal, the divider is measured to be operated from 40 to 90 GHz. Phase noise measurements of a 90 GHz input clock signal indicate ideal behavior with no measurable noise contribution from the divider. The divider followed by a buffer that can deliver more than-10 dBm output power, which is sufficient to drive succeeding stage. To the author's knowledge, the divider exhibits a competitive power dissipation and the highest FOM among silicon based frequency dividers that operating higher than 70 GHz.

Design of 0.18 μm CMOS programmable frequency divider based on standard cells

The design of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for transmitter and receiver in IEEE 802. 11 a standard, is investigated. The main steps in very large-scale integration （VLSI） design flow such as logic synthesis, floorplan and placement ＆ routing （P ＆ R） are introduced. By back-annotating the back-end information to the front-end design, the custom wire-load model is created and used for optimizing the design flow under deep submicron technology. The programmable frequency divider is implemented based on Artisan TSMC （Taiwan Semicoductor Manufacturing Co. Ltd. ）0. 18μm CMOS （complementary metal-oxide-semiconductor） standard cells and fabricated. The Chip area is 1 360. 5μm^2 and can work in the range of 100 to 200 MHz. The measurement results indicate that the design conforms to the frequency division precision.

A fractional frequency divider based on phase switching and negative feedback delta-sigma modulator for MMMS applications

A fractional frequency divider based on phase switching and negative feedback delta-sigma modulator(NF-DSM) is presented. The phase switching circuit, realized by switching 8 signals generated by a divider-by-4 circuit, is adopted to reduce the frequency division step. The NF-DSM, which can obtain smooth output spectra, is proposed to generate the fractional part of the division ratio, moreover, the integer part of the division ratio is realized by a divider-by-2/3 circuit chain. Fabricated in TSMC 0.18 μm RF CMOS technology, the fractional frequency divider achieves a measured operation frequency from 0.5 GHz to 8 GHz. With a 1.8 V supply voltage, the maximum current consumption of the whole divider is 17.5 mA, and the chip area is 0.58 mm^2, including the pads.

Residual Phase Noise and Time Jitters of Single-Chip Digital Frequency Dividers

In this paper, we demonstrate the residual phase noise of a few microwave frequency dividers which usually limit the performance of frequency synthesizers. In order to compare these dividers under different operation frequencies, we calculate additional time jitters of these dividers by using the measured phase noise. The time jitters are various from -0.1 fs to 43 fs in a bandwidth from 1 Hz to 100 Hz in dependent of models and operation frequencies. The HMC series frequency dividers exhibit outstanding performance for high operation frequencies, and the time jitters can be sub-fs. The time jitters of SP8401, MC10EP139, and MC100LVEL34 are comparable or even below that of HMC series for low operation frequencies.

INJECTION-LOCKED DIVIDER

An injection-Locked divider(ILD)can provide good synchronization at lower inputsignal to noise ratio,which is its advantage over other types of divider.The general expressionof phase equation and equivalent model are presented for the ILD with an input additive noise.In the absence of noise the performance of the phase-modulated signal through the ILD andsynchronous ranges of the ILD are given.The effects of the additive noise on the ILD arediscuued.The injection-locked amplifier(ILA)is only a particular case in which n=1,thereforethe given results arc applicable to the ILA.

A 0.35μm CMOS 6.1GHz 1∶4 Static Frequency Divider

A 1∶4 static frequency divider has been designed and realized in a 0.35-micron standard CMOS technology. The chip consists of two identical 1∶2 divider cells, which are based on SCL (Source Coupled Logic) flip-flops. By revising the traditional topology of SCL flip-flop, we get a divider with better performances. Measurement results show that the whole chip achieves the frequency division at more than 6GHz. Each 1∶2 divider consumes 11mW from a 3.3V supply. The divider can be used in RF and Optic-fiber Transceivers and other high-speed systems.

A new type of Wilkinson dual-frequency power divider with symmetrical transmission line stubs

To realize equal power splitting at two arbitrary gigahertz-frequencies, this paper presents a new type of Wilkinson dual frequency power divider, consisting of three-section transmission lines and a series RLC(resistor, inductor and capacitor)circuit. By equating the [ABCD] matrix of the proposed circuit to that of the quarter-wave impedance transformer, coupled with even/odd mode analyses, the design equations of the proposed network are derived. For verification, two dual-frequency power dividers with dual-band operating frequencies at 0.6 GHz and 3.0 GHz, and 3.8 GHz and 10 GHz respectively are designed and simulated. Simulation results show that the dual-band ratio of the proposed power divider can be as large as 5. Comparisons of the simulation results at X-band and S-band with different power dividers indicate that the proposed dual-band power divider performs better under the scenario of the upper operating frequency extending to X-band.

Design of Down Scalers in Mixed-Signal GHz Frequency Synthesizer

An optimized method is presented to design the down scalers in a GHz frequency synthesizer. The down scalers are comprised of dual modulus prescaler （DMP） and programmable ＆ pulse swallow divider,different methods of high frequency analog circuit and digital logical synthesis are adopted respectively. Using a DMP high speed, lower jitter and lower power dissipation are obtained,and output frequency of 133.0MHz of the DMP working at divide-by-8 shows an RMS jitter less than 2ps. The flexibility and reusability of the progrs, mmable divider is high;its use could be extended to many complicated frequency synthesizers. By comparison,it is a better design on performance of high-frequency circuit and good design flexibility.

Key technologies of frequency-hopping frequency synthesizer for Bluetooth RF front-end

A scheme of a frequency-hopping frequency-synthesizer applied to a Bluetooth ratio frequency （RF） front-end is presented,and design of a voltage controlled oscillator （VCO） and dual-modulus prescaler are focused on.It is fabricated in a 0.18 μm mixed-signal CMOS （complementary metal-oxide-semiconductor transistor） process.The power dissipation of VCO is low and a stable performance is gained.The measured phase noise of VCO at 2.4 GHz is less than -114.32 dBc/Hz.The structure of the DMP is optimized and a novel D-latch integrated with ＂OR＂ logic gate is used.The measured results show that the chip can work well under a 1.8 V power supply.The power dissipation of the core part in a dual modulus prescaler is only 5.76 mW.An RMS jitter of 2 ps is measured on the output signal at 118.3 MHz.It is less than 0.02% of the clock period.

Frequency synthesizer for DRM/DAB/AM/FM RF front-end

This paper describes a wideband low phase noise frequency synthesizer.It operates in the multi-band including digital radio mondiale DRM digital audio broadcasting DAB amplitude modulation AM and frequency modulation FM .In order to cover the signals of the overall frequencies a novel frequency planning and a new structure are proposed. A wide-band low-phase-noise low-power voltage-control oscillator VCO and a high speed wide band high frequency division ratio pulse swallow frequency divider with a low power consumption are presented.The monolithic DRM/DAB/AM/FM frequency synthesizer chip is also fabricated in a SMIC＇s 0.18-μm CMOS process.The die area is 1 425 μm ×795 μm including the test buffer and pads. The measured results show that the VCO operating frequency range is from 2.22 to 3.57 GHz the measured phase noise of the VCO is 120.22 dBc/Hz at 1 MHz offset the pulse swallow frequency divider operation frequency is from 0.9 to 3.4 GHz.The phase noise in the phase-locked loop PLL is-59.52 dBc/Hz at 10 kHz offset and fits for the demand of the DRM/DAB/AM/FM RF front-end. The proposed frequency synthesizer consumes 47 mW including test buffer under a 1.8 V supply.

基于分频器理论的新能源电网暂态频率稳定分析方法

在分析输配电线路频率相关参数时,将频率固定为额定值的时域仿真法是电力系统暂态频率稳定分析的常用方法。然而,随着新能源比例不断提升,电网各节点频率时空分布差异更为显著,已有传统数值微分频率分析方法难以保证分析精度。因此,文中提出一种基于分频器理论的新型电力系统暂态频率分析方法。与传统频率分析方法相比,该方法所得节点频率可随节点间电气距离变化而改变,在暂态过程中可更准确地刻画瞬态条件,实现各节点实时频率准确获取。通过建立简单含风电的三端系统,分析了基于分频器理论的实现方式,通过仿真验证了所提方法的正确性和优越性,可为新型电力系统频率稳定分析和控制设计提供新的思路和参考方案。

一种基于低温共烧陶瓷技术的一分二功率分配器设计方法

从小型化的要求出发,提出一种一分二等分功率分配器设计方法。以Wilkinson功率分配器结构为基础,将传统功率分配器中的直线型传输线改为螺旋线型传输线。采用低温共烧陶瓷(LTCC)技术进行小型化功率分配器设计,建模时利用立体叠层结构对功率分配器内部的传输线进行布局,内部不同金属层之间使用垂直通孔连接,使得该功率分配器尺寸与传统平面结构功率分配器相比大幅减小。在HFSS软件中完成三维模型建立与电磁仿真,并对设计完成的功率分配器进行加工测试,最终得到该功率分配器回波损耗优于19 dB,插入损耗优于3.5 dB,中心频率2.8 GHz处隔离度优于35 dB,具有较好的隔离度,满足一分二等分功率分配器的性能要求,并且LTCC功率分配器尺寸仅3.18 mm×1.58 mm×0.911 mm。