In multi-user multiple input multiple output （MU-MIMO） systems, the outdated channel state information at the transmit- ter caused by channel time variation has been shown to greatly reduce the achievable ergodic su...In multi-user multiple input multiple output （MU-MIMO） systems, the outdated channel state information at the transmit- ter caused by channel time variation has been shown to greatly reduce the achievable ergodic sum capacity. A simple yet effec- tive solution to this problem is presented by designing a channel extrapolator relying on Karhunen-Loeve （KL） expansion of time- varying channels. In this scheme, channel estimation is done at the base station （BS） rather than at the user terminal （UT）, which thereby dispenses the channel parameters feedback from the UT to the BS. Moreover, the inherent channel correlation and the parsimonious parameterization properties of the KL expan- sion are respectively exploited to reduce the channel mismatch error and the computational complexity. Simulations show that the presented scheme outperforms conventional schemes in terms of both channel estimation mean square error （MSE） and ergodic capacity.展开更多
Low Voltage Differential Signaling (LVDS) has become a popular choice for high-speed serial links to conquer the bandwidth bottleneck of intra-chip data transmission. This paper presents the design and the implementat...Low Voltage Differential Signaling (LVDS) has become a popular choice for high-speed serial links to conquer the bandwidth bottleneck of intra-chip data transmission. This paper presents the design and the implementation of LVDS Input/Output (I/O) interface circuits in a standard 0.18 μm CMOS technology using thick gate oxide devices (3.3 V), fully compatible with LVDS standard. In the proposed transmitter, a novel Common-Mode FeedBack (CMFB)circuit is utilized to keep the common-mode output voltage stable over Process, supply Voltage and Temperature (PVT) variations. Because there are no area greedy resistors in the CMFB circuitry, the disadvantage of large die area in existing transmitter structures is avoided. To obtain sufficient gain, the receiver consists of three am- plifying stages: a voltage amplifying stage, a transconductance amplifying stage, and a transimpedance amplifying stage. And to exclude inner nodes with high RC time constant, shunt-shunt negative feedback is introduced in the receiver. A novel active inductor shunt peaking structure is used in the receiver to fulfill the stringent requirements of high speed and wide Common-Mode Input Region (CMIR) without voltage gain, power dissipation and silicon area penalty. Simulation results show that data rates of 2 Gbps and 2.5 Gbps are achieved for the transmitter and receiver with power con- sumption of 13.2 mW and 8.3 mW respectively.展开更多
基金supported by the National Natural Science Foundation of China (6096200161071088)+2 种基金the Natural Science Foundation of Fujian Province of China (2012J05119)the Fundamental Research Funds for the Central Universities (11QZR02)the Research Fund of Guangxi Key Lab of Wireless Wideband Communication & Signal Processing (21104)
文摘In multi-user multiple input multiple output （MU-MIMO） systems, the outdated channel state information at the transmit- ter caused by channel time variation has been shown to greatly reduce the achievable ergodic sum capacity. A simple yet effec- tive solution to this problem is presented by designing a channel extrapolator relying on Karhunen-Loeve （KL） expansion of time- varying channels. In this scheme, channel estimation is done at the base station （BS） rather than at the user terminal （UT）, which thereby dispenses the channel parameters feedback from the UT to the BS. Moreover, the inherent channel correlation and the parsimonious parameterization properties of the KL expan- sion are respectively exploited to reduce the channel mismatch error and the computational complexity. Simulations show that the presented scheme outperforms conventional schemes in terms of both channel estimation mean square error （MSE） and ergodic capacity.
文摘Low Voltage Differential Signaling (LVDS) has become a popular choice for high-speed serial links to conquer the bandwidth bottleneck of intra-chip data transmission. This paper presents the design and the implementation of LVDS Input/Output (I/O) interface circuits in a standard 0.18 μm CMOS technology using thick gate oxide devices (3.3 V), fully compatible with LVDS standard. In the proposed transmitter, a novel Common-Mode FeedBack (CMFB)circuit is utilized to keep the common-mode output voltage stable over Process, supply Voltage and Temperature (PVT) variations. Because there are no area greedy resistors in the CMFB circuitry, the disadvantage of large die area in existing transmitter structures is avoided. To obtain sufficient gain, the receiver consists of three am- plifying stages: a voltage amplifying stage, a transconductance amplifying stage, and a transimpedance amplifying stage. And to exclude inner nodes with high RC time constant, shunt-shunt negative feedback is introduced in the receiver. A novel active inductor shunt peaking structure is used in the receiver to fulfill the stringent requirements of high speed and wide Common-Mode Input Region (CMIR) without voltage gain, power dissipation and silicon area penalty. Simulation results show that data rates of 2 Gbps and 2.5 Gbps are achieved for the transmitter and receiver with power con- sumption of 13.2 mW and 8.3 mW respectively.
