Carbon nanotube integrated circuit technology:purification,assembly and integration

As the manufacturing process of silicon-based integrated circuits(ICs)approaches its physical limit,the quantum effect of silicon-based field-effect transistors(FETs)has become increasingly evident.And the burgeoning carbon-based semiconductor technology has become one of the most disruptive technologies in the post-Moore era.As one-dimensional nanomaterials,carbon nanotubes(CNTs)are far superior to silicon at the same technology nodes of FETs because of their excellent electrical transport and scaling properties,rendering them the most competitive material in the next-generation ICs technology.However,certain challenges impede the industrialization of CNTs,particularly in terms of material preparation,which significantly hinders the development of CNT-based ICs.Focusing on CNT-based ICs technology,this review summarizes its main technical status,development trends,existing challenges,and future development directions.

Pixelated non-volatile programmable photonic integrated circuits with 20-level intermediate states

Multi-level programmable photonic integrated circuits(PICs)and optical metasurfaces have gained widespread attention in many fields,such as neuromorphic photonics,opticalcommunications,and quantum information.In this paper,we propose pixelated programmable Si_(3)N_(4)PICs with record-high 20-level intermediate states at 785 nm wavelength.Such flexibility in phase or amplitude modulation is achieved by a programmable Sb_(2)S_(3)matrix,the footprint of whose elements can be as small as 1.2μm,limited only by the optical diffraction limit of anin-house developed pulsed laser writing system.We believe our work lays the foundation for laser-writing ultra-high-level(20 levels and even more)programmable photonic systems and metasurfaces based on phase change materials,which could catalyze diverse applications such as programmable neuromorphic photonics,biosensing,optical computing,photonic quantum computing,and reconfigurable metasurfaces.

A Thermal-Conscious Integrated Circuit Power Model and Its Impact on Dynamic Voltage Scaling Techniques

We propose a novel thermal-conscious power model for integrated circuits that can accurately predict power and temperature under voltage scaling. Experimental results show that the leakage power consumption is underestimated by 52 % if thermal effects are omitted. Furthermore, an inconsistency arises when energy and temperature are simultaneously optimized by dynamic voltage scaling. Temperature is a limiting factor for future integrated circuits,and the thermal optimization approach can attain a temperature reduction of up to 12℃ with less than 1.8% energy penalty compared with the energy optimization one.

Digitalized analog integrated circuits

Digital integrated circuits have significantly benefited from technology scaling down,while conventional analog integrated circuits suffer from more design constraints.In recent years,there has been strong research interest in replacing conventional analog blocks with digitally-friendly and digitally-intensive alternatives,while signif-icant progress has been made.This paper reviews the existing digitalized analog integrated circuits,including amplifiers,analog-to-digital converters,phase-locked loops,and power supplies.Based on the review,the future development trends of the digitalized analog integrated circuits are derived.

A Single-Board Integrated Millimeter-Wave Asymmetric Full-Digital Beamforming Array for B5G/6G Applications

In this article,a single-board integrated millimeter-wave(mm-Wave)asymmetric full-digital beamforming(AFDBF)array is developed for beyond-fifth-generation(B5G)and sixth-generation(6G)communications.The proposed integrated array effectively addresses the challenge of arranging a large number of ports in a full-digital array by designing vertical connections in a three-dimensional space and successfully integrating full-digital transmitting(Tx)and receiving(Rx)arrays independently in a single board.Unlike the traditional symmetric array,the proposed asymmetric array is composed of an 8×8 Tx array arranged in a square shape and an 8+8 Rx array arranged in an L shape.The center-to-center distance between two adjacent elements is 0.54k0 for both the Tx and Rx arrays,where k0 is the free-space wavelength at 27 GHz.The proposed AFDBF array possesses a more compact structure and lower system hardware cost and power consumption compared with conventional brick-type full-digital arrays.In addition,the energy efficiency of the proposed AFDBF array outperforms that of a hybrid beamforming array.The measurement results indicate that the operating frequency band of the proposed array is 24.25–29.50 GHz.An eight-element linear array within the Tx array can achieve a scanning angle ranging from-47°to+47°in both the azimuth and the elevation planes,and the measured scanning range of each eight-element Rx array is–45°to+45°.The measured maximum effective isotropic radiated power(EIRP)of the eight-element Tx array is 43.2 dBm at 28.0 GHz(considering the saturation point).Furthermore,the measured error vector magnitude(EVM)is less than 3%when 64-quadrature amplitude modulation(QAM)waveforms are used.

Ultra-Low Linewidth Frequency Stabilized Integrated Lasers: A New Frontier in Integrated Photonics

With the advancement of photonic integration technology,ultra-low linewidth frequency-stabilized lasers have demonstrated significant potential in precision measurement,quantum communication,atomic clocks,etc.This review summarizes the latest developments in integrated photonics for achieving ultra-low linewidth lasers,particularly breakthroughs made by integrating Brillouin lasers.We discuss the design principles,manufacturing processes,performance characteristics,and potential value of these lasers in various applications.

Test system of the front-end readout for an application-specific integrated circuit for the water Cherenkov detector array at the large high-altitude air shower observatory

The water Cherenkov detector array(WCDA) is an important part of the large high-altitude air shower observatory(LHAASO),which is in a research and development phase.The central scientific goal of LHAASO is to explore the origin of high-energy cosmic rays of the universe and to push forward the frontier of new physics.To simplify the WCDA's readout electronics,a prototype of a front-end readout for an application-specific integrated circuit(ASIC) is designed based on the timeover-threshold method to achieve charge-to-time conversion.High-precision time measurement and charge measurement are necessary over a full dynamic range[1-4000photoelectrons(P.E.)].To evaluate the performance of this ASIC,a test system is designed that includes the front-end ASIC test module,digitization module,and test software.The first module needs to be customized for different ASIC versions,whereas the digitization module and test software are tested for general-purpose use.In the digitization module,a field programmable gate array-based time-todigital converter is designed with a bin size of 333 ps,which also integrates an inter-integrated circuit to configure the ASIC test module,and a universal serial bus interface is designed to transfer data to the remote computer.Test results indicate that the time resolution is better than 0.5 ns,and the charge resolution is better than 30%root mean square(RMS) at 1 P.E.and 3%RMS at 4000 P.E.,which are beyond the application requirements.

Through-silicon-via crosstalk model and optimization design for three-dimensional integrated circuits

Through-silicon-via （TSV） to TSV crosstalk noise is one of the key factors affecting the signal integrity of three- dimensional integrated circuits （3D ICs）. Based on the frequency dependent equivalent electrical parameters for the TSV channel, an analytical crosstalk noise model is established to capture the TSV induced crosstalk noise. The impact of various design parameters including insulation dielectric, via pitch, via height, silicon conductivity, and terminal impedance on the crosstalk noise is analyzed with the proposed model. Two approaches are proposed to alleviate the TSV noise, namely, driver sizing and via shielding, and the SPICE results show 241 rnV and 379 mV reductions in the peak noise voltage, respectively.

High density Al2O3/TaN-based metal-insulatormetal capacitors in application to radio equency integrated circuits

Metal-insulator-metal （MIM） capacitors with atomic-layer-deposited Al2O3 dielectric and reactively sputtered TaN electrodes in application to radio frequency integrated circuits have been characterized electrically. The capacitors exhibit a high density of about 6.05 fF/μm^2, a small leakage current of 4.8 × 10^-8 A/cm^2 at 3 V, a high breakdown electric field of 8.61 MV/cm as well as acceptable voltage coefficients of capacitance （VCCs） of 795 ppm/V2 and 268ppm/V at 1 MHz. The observed properties should be attributed to high-quality Al2O3 film and chemically stable TaN electrodes. Further, a logarithmically linear relationship between quadratic VCC and frequency is observed due to the change of relaxation time with carrier mobility in the dielectric. The conduction mechanism in the high field ranges is dominated by the Poole-Frenkel emission, and the leakage current in the low field ranges is likely to be associated with trap-assisted tunnelling. Meanwhile, the Al2O3 dielectric presents charge trapping under low voltage stresses, and defect generation under high voltage stresses, and it has a hard-breakdown performance.

Hybrid material integration in silicon photonic integrated circuits

Hybrid integration ofⅢ-Ⅴand ferroelectric materials is being broadly adopted to enhance functionalities in silicon photonic integrated circuits(PICs).Bonding and transfer printing have been the popular approaches for integration of III–V gain media with silicon PICs.Similar approaches are also being considered for ferroelectrics to enable larger RF modulation bandwidths,higher linearity,lower optical loss integrated optical modulators on chip.In this paper,we review existing integration strategies ofⅢ-Ⅴmaterials and present a route towards hybrid integration of bothⅢ-Ⅴand ferroelectrics on the same chip.We show that adiabatic transformation of the optical mode between hybrid ferroelectric and silicon sections enables efficient transfer of optical modal energies for maximum overlap of the optical mode with the ferroelectric media,similar to approaches adopted to maximize optical overlap with the gain section,thereby reducing lasing thresholds for hybridⅢ-Ⅴintegration with silicon PICs.Preliminary designs are presented to enable a foundry compatible hybrid integration route of diverse functionalities on silicon PICs.

High performance integrated photonic circuit based on inverse design method

The basic indexes of all-optical integrated photonic circuits include high-density integration,ultrafast response and ultralow energy consumption.Traditional methods mainly adopt conventional micro/nano-structures.The overall size of the circuit is large,usually reaches hundreds of microns.Besides,it is difficult to balance the ultrafast response and ultra-low energy consumption problem,and the crosstalk between two traditional devices is difficult to overcome.Here,we propose and experimentally demonstrate an approach based on inverse design method to realize a high-density,ultrafast and ultra-low energy consumption integrated photonic circuit with two all-optical switches controlling the input states of an all-optical XOR logic gate.The feature size of the whole circuit is only 2.5μm×7μm,and that of a single device is 2μm×2μm.The distance between two adjacent devices is as small as 1.5μm,within wavelength magnitude scale.Theoretical response time of the circuit is 150 fs,and the threshold energy is within 10 fJ/bit.We have also considered the crosstalk problem.The circuit also realizes a function of identifying two-digit logic signal results.Our work provides a new idea for the design of ultrafast,ultra-low energy consumption all-optical devices and the implementation of high-density photonic integrated circuits.

Science Letters:The Moore’s Law for photonic integrated circuits

We formulate a “Moore’s law” for photonic integrated circuits (PICs) and their spatial integration density using two methods. One is decomposing the integrated photonics devices of diverse types into equivalent basic elements, which makes a comparison with the generic elements of electronic integrated circuits more meaningful. The other is making a complex compo- nent equivalent to a series of basic elements of the same functionality, which is used to calculate the integration density for func- tional components realized with different structures. The results serve as a benchmark of the evolution of PICs and we can con- clude that the density of integration measured in this way roughly increases by a factor of 2 per year. The prospects for a continued increase of spatial integration density are discussed.

Human blood plasma-based electronic integrated circuit amplifier configuration

Dear Editor： There is accumulating evidence that human blood electronic circuit components and their application circuits become more and more important to cyborg implant/engineering, man-machine interface, hu- man disease detection and healing, and artificial brain evolutionusl. Here, we report the first development of human plasma-based amplifier circuit in the dis- crete as well as integrated circuit （IC） configuration mode. Electrolytes in the human blood contain an enormous number of charge carriers such as positive and negative molecule/atom ions, which are electri- cally conducting media and therefore can be utilized for developing electronic circuit components and their application circuits. These electronic circuits obvi- ously have very high application impact potential towards bio-medical engineering and medical science and technology.

A 330-500 GHz Zero-Biased Broadband Tripler Based on Terahertz Monolithic Integrated Circuits

A 330-500 GHz zero-biased broadband monolithic integrated tripler is reported. The measured results show that the maximum efficiency and the maximum output power are 2% and 194μW at 348 GHz. The saturation characteristic test shows that the output i dB compression point is about -8.5 dBm at 334 GHz and the maximum efficiency is obtained at the point, which is slightly below the 1 dB compression point. Compared with the conventional hybrid integrated circuit, a major advantage of the monolithic integrated circuit is the significant improvement of reliability and consistency. In this work, a terahertz monolithic frequency multiplier at this band is designed and fabricated.

Fabrication of integrated resistors in printed circuit boards

In order to utilize integrated passive technology in printed circuit boards （PCBs）, manufacturing processing for integrated resistors by lamination method was investigated. Integrated resistors fabricated from Ohmega technologies in the experiment were 1 408 pieces per panel with four different patterns A, B, C and D and four resistance values of 25, 50, 75 and 100 fL Six panel per batch and four batches were performed totally. The testing was done for 960 pieces of integrated resistors randomly selected with the same size. The value distribution ranges and the relative standard deviation （RSD） show that the scatter degree of the resistance decreases with the resistor size increasing and/or with the resistance increasing. Patterns D with resistance of 75 and 100% for four patterns have the resistance value variances less than 10%. Patterns C and D with resistance of 100 Ω have the manufacturing tolerance less than 10%. The process capabilities are from about 0.6 to 1.6 for the designed testing patterns, which shows that the integrated resistors fabricated have the potential to be used in multilayer PCBs in the future.

Current Status of the Integrated Circuit Industry in China--IC Manufacturing Industry

Editorial Introduction: China's IC industry has been flourishing in recent years, huge market demand together with government investments are the major driving forces for this development. The status and development momentum of the Chinese IC industry also attracted wide interest and attention of international counterparts. A group of domestic IC experts are invited by the JoMM to write a series of articles about China's IC industry, including the history, current status, development, and related government policies. Information in these articles is all from public data from recent years. The purpose of these articles is to enhance mutual understanding between the Chinese domestic IC industry and international IC ecosystem. The following article is the third one of this series, the status quo of China's IC industry. The IC industry chain is very long including design, manufacturing, special equipment, materials, packaging and testing. The article series are arranged in accordance with this scope.

Image boundary extraction based on island model genetic algorithms for integrated circuit defect detection

The integrated circuit chip with high performance has a high sensitivity to the defects in manufacturing environments.When there are defects on a wafer,the defects may lead to the degradation of chip performance.It is necessary to design effective detection approaches for the defects in order to ensure the reliability of wafer.In this paper,a new method based on image boundary extraction is presented for the detection of defects on a wafer.The method uses island model genetic algorithms to perform the segmentation of wafer images,and gets the optimal threshold values.The island model genetic algorithm uses two distinct subpopulations,it is a coarse grain parallel model.The individuals migration can occur between the two subpopulations to share genetic materials.A lot of experimental results show that the defect detection method proposed in this paper can obtain the features of defects effectively.

Precision photonic integration for future large-scale photonic integrated circuits

Since the proposal of the concept of photonic integratedcircuits (PICs), tremendous progress has been made. In2005, Infinera Corp. rolled out the first commercial PICs, inwhich hundreds of optical functions were integrated onto asmall form factor chip for wavelength division multiplexing(WDM) systems[1], then a monolithically integrated 10 ×10 Gb/s WDM chip has been demonstrated, the channelnumber is ten[2]. Like ICs, large-scale PICs (LS-PICs) will besure to be pursued. However, there are still some generalchallenges associated with LS-PICs. The challenges for III–V(mainly InP) PICs is the semiconductor process, which is notmature for LS-PICs. Up to now, the channel number in commercialIII–V WDM PICs by Infinera is still about ten or less.For silicon photonics, the challenge is the silicon based lightsource. The low cost and mature solution for silicon lasers isstill unavailable and only 4 × 25 Gb/s PICs are deployed byIntel Corp. after 18-year R&D investment. Thus it is still unavailablefor practical LS-PICs in the present times.

METHOD OF PARAMETER STATISTICAL ANALYSIS FOR BIPOLAR INTEGRATED CIRCUIT DESIGN

The method and procedure of realizing parameter statistical correlation analysis ofbipolar analog IC’s are given,and the statistical model of parameter are constructed with doubleparameters(B_F,R_S).Based on the comparison and analysis of the circuit characteristics,it isshown that the method can be used for analysis and design of bipolar IC’s.

ANALYSIS OF THE TRANSMISSION PROPERTIES OF TAPERED MUTLICONDUCTOR INTERCONNECTING BUSES IN HIGH-SPEED INTEGRATED CIRCUITS

Analysis approach and formulas for the transmission properties of uniform multicon-ductor interconnecting buses in high-speed integrated circuits are presented in this article. And further, by using a network approach, a tapered bus system can be analyzed as a set of cascaded uniform buses with slightly different strip widths. Obtained results are in good agreement with the experimental data.