Structured Illumination Chip Based on Integrated Optics

A compact structured illumination chip based on integrated optics is proposed and fabricated on a silicon-on- insulator platform. Based on the simulation of Caussian beam interference, we adopt a chirped diffraction grating to achieve a specific interference pattern. The experimental results match well with the simulations. The portability and flexibility of the structured illumination chip can be increased greatly through horizontal encapsulation. High levels of integration, compared with the conventional structured illumination approach, make this chip very compact, with a footprint of only around 1 mm2. The chip has no optical lenses and can be easily combined with a microfluidic system. These properties would make the chip very suitable for portable 3D scanner and compact super-resolution microscopy applications.

A New Method for Optimizing Layout Parameter ofan Integrated On-Chip Inductor in CMOSRF IC's

Analyzing the influence on Q factor, which was caused by the parasitic effect in a CMOS RF on chip integrated inductor, a concise method to increase the Q factor has been obtained when optimizing the layout parameter. Using this method, the Q factor of 7.9 can be achieved in a 5nH inductor (operating frequency is 2GHz) while the errors in inductance are less than 0.5% compared with the aimed values. It is proved by experiments that this method can guarantee the sufficient accuracy but require less computation time. Therefore, it is of great use for the design of the inductor in CMOS RF IC’s.

Hybrid-integrated chalcogenide photonics

High-quality photonic materials are critical for promoting integrated photonic devices with broad bandwidths,high efficiencies,and flexibilities for high-volume chip-scale fabrication.Recently,we designed a home-developed chalcogenide glass(ChG)-Ge_(25)Sb_(10)S_(65)(GeSbS)for optical information processing chips and systems,which featured an ultrabroad transmission window,a high Kerr nonlinearity and photoelastic coefficient,and compatibility with the photonic hybrid integration technology of silicon photonics.Chip-integrated GeSbS microresonators and microresonator arrays with high quality factors and lithographically controlled fine structures were fabricated using a modified nanofabrication process.Moreover,considering the high Kerr nonlinearity and photoelastic effect of ChGs,we realised a novel ChG hybrid integrated chip,inspired by recent advances in integrated soliton microcombs and acousto-optic(AO)modulators.

A pair of integrated optoelectronic transceiving chips for optical interconnects

In this Letter, a pair of integrated optoelectronic transceiving chips is proposed. They are constructed by integrating a vertical cavity surface emitting laser unit above a positive-intrinsic-negative photodetector unit. One of the transceiving chips emits light at the wavelength of 848.1 nm with a threshold current of 0.8 mA and a slope efficiency of 0.81 W/A. It receives light between 801 and 814 nm with a quantum efficiency of higher than 70%. On its counterpart, the other one of the transceiving chips emits light at the wavelength of 805.3 nm with a threshold current of 1.1 mA and a slope efficiency of 0.86 W/A. It receives light between 838 and 855 nm with a quantum efficiency of higher than 70%. The proposed pair of integrated optoelectronic transceiving chips can work full-duplex with each other, and they can be applied to single fiber bidirectional optical interconnects.

60 GHz SIW Steerable Antenna Array in LTCC

In this paper, we present a 60 GHz substrate-integrated waveguide fed-steerable low-temperature cofired ceramics array. The antenna is suitable for transmitting and receiving on the 60 GHz wireless personal area network frequency band. The wireless system can be used for HDTV, high-data-rate networking up to 4.5 GBit/s, security and surveillance, and similar applications.

A Low Power Non-Volatile LR-WPAN Baseband Processor with Wake-Up Identification Receiver

The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power management module.The main receiver adopts a unified simplified synchronization method and channel codec with proactive Reed-Solomon Bypass technique,which increases the robustness and energy efficiency of receiver.The WUI receiver specifies the communication node and wakes up the transceiver to reduce average power consumption of the transceiver.The embedded NVM can backup/restore the states information of processor that avoids the loss of the state information caused by power failure and reduces the unnecessary power of repetitive computation when the processor is waked up from power down mode.The baseband processor is designed and verified on a FPGA board.The simulated power consumption of processor is 5.1uW for transmitting and 28.2μW for receiving.The WUI receiver technique reduces the average power consumption of transceiver remarkably.If the transceiver operates 30 seconds in every 15 minutes,the average power consumption of the transceiver can be reduced by two orders of magnitude.The NVM avoids the loss of the state information caused by power failure and energy waste caused by repetitive computation.

Simultaneous evaluation of two branches of a multifunctional integrated optic chip with an ultra-simple dual-channel configuration

We propose an ultra-simple dual-channel configuration for simultaneously evaluating two branches of a multifunctional integrated optic chip(MFIOC). In the configuration, the MFIOC is employed as a beam splitter to construct the demodulation interferometer together with a 2 × 2 fiber coupler. Interference happens between polarization modes traveling through different channels of the MFIOC. The cross-couplings of each channel are respectively characterized by the interference peaks which distribute on opposite sides of the central interference peak. Temperature responses of the MFIOC are experimentally measured from-40°C to 80°C. Results show that the proposed configuration can achieve simultaneous dual-channel transient measurements with resolution of-90 d B and dynamic range of 90 d B. In addition, the two channels of the configuration have consistent measuring performance, and the two branches of the MFIOC have different responses to temperature variation.

CMOS vision sensor with fully digital image process integrated into low power 1/8-inch chip

A digital still camera image processing system on a chip, different from the video camera system, is pre- sented for mobile phone to reduce the power consumption and size. A new color interpolation algorithm is proposed to enhance the image quality. The system can also process fixed patten noise （FPN） reduction, color correction, gamma correction, RGB/YUV space transfer, etc. The chip is controlled by sensor regis- ters by inter-integrated circuit （I2C） interface. The voltage for both the front-end analog and the pad cir- cuits is 2.8 V, and the volatge for the image signal processing is 1.8 V. The chip running under the external 13.5-MHz clock has a video data rate of 30 frames/s and the measured power dissipation is about 75 roW.