Microwave Integrated Circuit Design Handbook

作者:Reinmut K.Hoffmann(1984 IEEE微波奖获得者) 出版:Artech House公司(美国)1987年本书给出适于微波工程师和研究人员应用的有关MIC方面的基础技术、电性能和设计。侧重于电性能分析和设计,强调应用。对于每一种设计技术和应用均作出较清楚的叙述和完整的处理。本书尽量给出电路的物理描述,避免过于冗长的数学公式,内容包含对下列议题的详细评述与研讨:

High performance integrated photonic circuit based on inverse design method

The basic indexes of all-optical integrated photonic circuits include high-density integration,ultrafast response and ultralow energy consumption.Traditional methods mainly adopt conventional micro/nano-structures.The overall size of the circuit is large,usually reaches hundreds of microns.Besides,it is difficult to balance the ultrafast response and ultra-low energy consumption problem,and the crosstalk between two traditional devices is difficult to overcome.Here,we propose and experimentally demonstrate an approach based on inverse design method to realize a high-density,ultrafast and ultra-low energy consumption integrated photonic circuit with two all-optical switches controlling the input states of an all-optical XOR logic gate.The feature size of the whole circuit is only 2.5μm×7μm,and that of a single device is 2μm×2μm.The distance between two adjacent devices is as small as 1.5μm,within wavelength magnitude scale.Theoretical response time of the circuit is 150 fs,and the threshold energy is within 10 fJ/bit.We have also considered the crosstalk problem.The circuit also realizes a function of identifying two-digit logic signal results.Our work provides a new idea for the design of ultrafast,ultra-low energy consumption all-optical devices and the implementation of high-density photonic integrated circuits.

Concise Modeling of Amorphous Dual-Gate In-Ga-Zn-O Thin-Film Transistors for Integrated Circuit Designs

An analytical model for current-voltage behavior of amorphous In-Ga-Zn-O thin-film transistors（a-IGZO TFTs）with dual-gate structures is developed.The unified expressions for synchronous and asynchronous operating modes are derived on the basis of channel charges,which are controlled by gate voltage.It is proven that the threshold voltage of asynchronous dual-gate IGZO TFTs is adjusted in proportion to the ratio of top insulating capacitance to the bottom insulating capacitance（C_（TI）/C_（BI））.Incorporating the proposed model with Verilog-A,a touch-sensing circuit using dual-gate structure is investigated by SPICE simulations.Comparison shows that the touch sensitivity is increased by the dual-gate IGZO TFT structure.

Matching processing in the design of integrated circuits

In the design of the integrated circuits, in order to ensure that the designed products conform to the presupposed parameters, while designing the schematic diagrams of the circuits, we should also strengthen the layout design. Especially in the design of the analog circuits, in the layout design, there is a high degree of matching requirement for the MOS. It will have an important impact on the performance of the chips. Based on this perspective, the author of this paper analyzes how to realize the matching of the three aspects of the MOS, the resistance and the capacitance in the integrated circuit design, in order to avoid the problem of the mismatch due to the arts and crafts.

Design, Fabrication, and Modeling of CMOS-Compatible Double Photodiode

A double photodiode (PD) constructed by p+/N-well junction and N-well/p-sub junction was designed and fabricated in a UMC 0.18-μm CMOS process. Based on the device structure and mechanism of double PD, a novel small-signal equivalent circuit model considering the carrier transit effect and the parasitic RC time constant was presented. By this model with complete electronic components, the double PD can be incorporated in a commercial circuit simulator. The component values were extracted by fitting the measured S-parameters using simulated annealing algorithm, and a good agreement between the measurement and the simulation results was achieved. © 2017, Tianjin University and Springer-Verlag Berlin Heidelberg.

Challenges and opportunities toward fully automated analog layout design

Realizing the layouts of analog/mixed-signal(AMS)integrated circuits(ICs)is a complicated task due to the high design flexibility and sensitive circuit performance.Compared with the advancements of digital IC layout automation,analog IC layout design is still heavily manual,which leads to a more time-consuming and error-prone process.In recent years,significant progress has been made in automated analog layout design with emerging of several open-source frameworks.This paper firstly reviews the existing state-of-the art AMS layout synthesis frameworks with focus on the different approaches and their individual challenges.We then present recent research trends and opportunities in the field.Finally,we summaries the paper with open questions and future directions for fully-automating the analog IC layout.

Integrating Universal Design Standards and Building Information Modeling at the Conceptual Design Stage of Buildings

A projection of the Canadian population shows that in 2024 one in five Canadians will be over 65 years old. This shift forces designers to consider the entire lifetime of occupants during the design of new buildings. Universal Design (UD), which is a design that accommodates all people to the greatest extent possible and aging in place design that is deeply rooted in the principles of UD, aim to house people irrespective of their age, ability, and chronic health conditions. Building Information Modeling (BIM) significantly helps advance the development of the Architecture, Engineering, and Construction (AEC) industry in a more collaborative and automated way. Integrating BIM and UD allows designers to incorporate UD standards easily and efficiently at the conceptual design stage of buildings by using the functionalities and capabilities of BIM tools. Therefore, this study presents the development of an automated computer model to facilitate the adoption of UD standards and processes. The novelty highlighted in this model resides in the creation of an automated method that employs a newly created plug-in and databases to assist designers to incorporate UD standards at the conceptual stage in a timely and cost-effective manner. Furthermore, the study introduces the methodology consisting of collecting, categorizing, and storing data from various universal design and accessible design guidelines in the developed databases and developing new plug-ins in BIM tool to link the developed databases in order to automate the process of retrieving necessary information and components to help designers and owners select optimal design alternatives based on their predefined criteria.

Design and Evaluation of SIMpliLife, an NFC Platform to Ease Day-to-Day Actions of People＇s Life

In this paper the authors describe the design, prototyping and evaluation of SIMpliLife, a framework for mobile phones with the aim of making people＇s life easier, providing day-to-day services such as payment, ticketing and information retrieval by means of NFC （Near Field Communication） technology. It was developed via the collaboration between two research labs of Sapienza University of Rome： the RFID （Radio Frequency Identification） Lab and the Usability and Accessibility Lab （LUA）, both belonging to CATTID （Centre for Applications of Teleservices and of Technologies for Innovation in Digital world） research centre. Technically, SIMpliLife is a SIM-based platform for NFC mobile phones that interfaces several applications able to manage the abovementioned services. The high-level User Interface has been developed by means of Smart Card Web Server （SCWS） technology, thus providing enhanced user experience if compared to traditional SIM-based implementations based on SIM Toolkit.

Design and Implementation of an Efficient Reversible Comparator Using TR Gate

Reversible logic is a new emerging technology with many promising applications in optical information processing, low power (Complementary Metal Oxide Semiconductor) CMOS design, (De Oxy RiboNucleic Acid) DNA computing, etc. In industrial automation, comparators play an important role in segregating faulty patterns from good ones. In previous works, these comparators have been implemented with more number of reversible gates and computational complexity. All these comparators use propagation technique to compare the data. This will reduce the efficiency of the comparators. To overcome the problem, this paper proposes an efficient comparator using (Thapliyal Ranganathan) TR gate utilizing full subtraction and half subtraction algorithm which will improve the computation efficiency. The comparator design using half subtraction algorithm shows an improvement in terms of quantum cost. The comparator design using full subtraction algorithm shows effectiveness in reducing number of reversible gates required and garbage output.

Challenges to Data-Path Physical Design Inside SOC

Previously,a single data-path stack was adequate for data-path chips,and the complexity and size of the data-path was comparatively small.As current data-path chips,such as system-on-a-chip (SOC),become more complex,multiple data-path stacks are required to implement the entire data-path.As more data-path stacks are integrated into SOC,data-path is becoming a critical part of the whole giga-scale integrated circuits (GSI) design.The traditional physical design methodology can not satisfy the data-path performance requirements,because it can not accommodate the data-path bit-sliced structure and the strict performance (such as timing,coupling,and crosstalk) constraints.Challenges in the data-path physical design are addressed.The fundamental problems and key technologies in data-path physical design are analysed.The corresponding researches and solutions in this research field are also discussed.

Trending IC design directions in 2022

For the non-stop demands for a better and smarter society, the number of electronic devices keeps increasing exponentially;and the computation power, communication data rate, smart sensing capability and intelligence are always not enough. Hardware supports software, while the integrated circuit(IC) is the core of hardware. In this long review paper, we summarize and discuss recent trending IC design directions and challenges, and try to give the readers big/cool pictures on each selected small/hot topics. We divide the trends into the following six categories, namely, 1) machine learning and artificial intelligence(AI) chips, 2) communication ICs, 3) data converters, 4) power converters, 5) imagers and range sensors, 6) emerging directions. Hope you find this paper useful for your future research and works.

Three-dimensional global interconnect based on a design window

Based on a stochastic wire length distributed model, the interconnect distribution of a three-dimensional integrated circuit （3D IC） is predicted exactly. Using the results of this model, a global interconnect design window for a giga-scale system-on-chip （SOC） is established by evaluating the constraints of 1） wiring resource, 2） wiring bandwidth, and 3） wiring noise. In comparison to a two-dimensional integrated circuit （2D IC） in a 130-nm and 45-nm technology node, the design window expands for a 3D IC to improve the design reliability and system performance, further supporting 3D IC application in future integrated circuit design.

模拟集成电路设计课程实验项目驱动式教学改革

基于高校模拟集成电路设计课程实验项目分散且教学目标不明确,缺乏系统性和工程应用性,提出了项目驱动式教学改革。以与企业合作的工程项目为基础设立实验项目,并分解成由易及难的多个实验题目,分阶段、分步骤完成实验内容,最终完成模拟集成电路设计全流程实验,以“带隙基准电压源芯片全定制设计实验”为例阐述了实施步骤。课程实验项目采用驱动式教学加深了学生对课程内容的理解,有助于培养学生扎实的工程实践能力。

一种基于模式布线的柔性电路板布线规划算法

为解决柔性电路板整板自动化布线算法布线效率低、布线效果较差的问题,提出基于模式布线的柔性电路板布线规划算法,采用模式布线近似拟合详细布线,缩小详细布线和布线规划之间的精度误差。同时,根据人工经验设计4种布线模式和若干扇出模式,模拟扇出区内部资源分配和扇出区间排列组合可能出现的情况。针对层分配问题,设计了根据当前布线结果以及未来对其他线网的影响综合评价的层分配算法,针对通道区不允许打孔的约束,根据通道连接扇出区的位置顺序求得通道内布线线网拓扑不交叉序列,并作为分割线上过点位置排列顺序约束。最后,综合比较每个模式下的结果,选择代价最小的结果作为最终布线规划的结果。使用多个工业用例进行测试,实验结果表明,与已有柔性电路板布线规划算法相比,本文布线规划算法可以提升详细布线效率和布线结果。

OBE 理念下“数字集成电路设计”课程教学改革

“数字集成电路设计”是微电子科学与工程专业重要的专业核心课。在课程中引入OBE教学理念,以学生毕业从事集成电路设计工作应达成的能力目标为导向,逆向设计课程教学方案。从课程理论讲授到工程项目案例教学,对学习目标达成情况进行跟踪并针对教学活动和目标持续改进,形成面向能力目标的教学效果评价体系。帮助学生独立解决科学与工程问题,锻炼了学生的工程实践能力和创新能力。

“教赛”一体“射频集成电路”研究生课程实践

针对新时代背景下研究生教育问题,以面向电子信息类相关研究生课程为对象,引入电子竞赛内容作为教学设计及工程实践,以赛促课,探索满足研究生创新能力培养模式要求的“教赛”一体研究生专业课程建设方法。以江苏大学电气信息工程学院开设的“射频集成电路”课程为例,将“研创赛”相关内容有机高效地融入课堂,在掌握理论知识的同时,有效提升研究生自主学习能力和创新实践能力。

FinFET/GAAFET/CFET纳电子学的研究进展

集成电路延续摩尔定律的发展正在从鳍栅场效应晶体管(FinFET)纳电子学时代向原子水平上的埃(?魡)时代转变。综述了该转变阶段的三大创新发展热点,FinFET、环栅场效应晶体管(GAAFET)和互补场效应晶体管(CFET)纳电子学的发展历程和最新进展。在FinFET纳电子领域综述并分析了当今Si基CMOS集成电路的发展现状,包含覆盖了22 nm、14 nm、10 nm、7 nm和5 nm 5个发展代次的创新特点和3 nm技术节点的创新和应用。在GAAFET纳电子学领域综述并分析了各类GAAFET的结构创新,2 nm技术节点的关键技术突破,3 nm技术节点的多桥沟道场效应晶体管技术平台创新与应用,以及GAAFET有关工艺、器件结构、电路和材料等方面的创新。在CFET纳电子学领域综述并分析了CFET技术在器件模型、堆叠工艺、单胞电路设计和三维集成等方面的创新,展现出CFET超越2 nm技术节点的发展新态势。

《集成电路版图设计》课程高职教育改革研究

本文的主要目的为分析《集成电路版图设计》课程高职教育改革的研究方式。通过分析高职集成电路版图设计课程中理念教学的改革方式,以及分析开展“1+X集成电路设计与验证”考证情况,包括分析开展高职技能大赛“集成电路开发应用”进一步提高研究质量,确保教学改革质量得到改善的状况。由此本文得出结论,当前做好《集成电路版图设计》课程高职教育改革研究能满足教学发展的需求,提高学生的学习质量。

“数字集成电路设计”教学方法研究与探索

当前安徽大学“数字集成电路设计”课程的开展存在诸多问题(如教学方法单一,验证性实验内容相对简单,实验课程考核机制单一等),因此教学方法亟须改进。针对课程的现状,立足于教学模式、教学内容和考核方式三个方面进行改革和探索,积极探索“新工科”背景下数字集成电路设计的教学新方法,提出采用线上线下混合式教学方式,激发学生的学习兴趣,致力于提高学生的主观能动性和创新能力。

模拟滤波器实验教学设计

为了促使学生较快掌握电子电路设计方法,设计了一个基于Multisim软件的模拟滤波器设计与应用的实验教学案例。该案例通过Multisim软件仿真不同类型的模拟滤波器电路,并对电路设计进行修正,使其更好地符合设计要求,用元器件在电路板上焊接实际电路,进行测试。设计的滤波电路满足特定频率、特定增益等要求,对理解实验原理的理解和滤波器的设计有促进作用。