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Analog Module Placement Design Using Genetic Algorithm
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作者 张理洪 谢长生 +1 位作者 裴先登 Ulrich Kleine 《Tsinghua Science and Technology》 SCIE EI CAS 2003年第2期161-168,共8页
This paper presents a novel genetic algorithm for analog module placement based on a generalization of the two-dimensional bin packing problem. The genetic encoding and operators assure that all problem constraints ar... This paper presents a novel genetic algorithm for analog module placement based on a generalization of the two-dimensional bin packing problem. The genetic encoding and operators assure that all problem constraints are always satisfied. Thus the potential problems of adding penalty terms to the cost function are eliminated so that the search configuration space is drastically decreased. The dedicated cost function is based on the special requirements of analog integrated circuits. A fractional factorial experiment was conducted using an orthogonal array to study the algorithm parameters. A meta-GA was applied to determine the optimal parameter values. The algorithm was tested with several local benchmark circuits. The experimental results show that the algorithm has better performance than the simulated annealing approach with satisfactory results comparable to manual placement. This study demonstrates the effectiveness of the genetic algorithm in the analog module placement problem. The algorithm has been successfully used in a layout synthesis tool. 展开更多
关键词 genetic algorithm PLACEMENT parameter optimization MODULE analog integrated circuit layout
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A Yield-Driven Gridless Router
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作者 周强 蔡懿慈 +1 位作者 李舵 洪先龙 《Journal of Computer Science & Technology》 SCIE EI CSCD 2007年第5期653-660,共8页
A new gridless router to improve the yield of IC layout is presented. The improvement of yield is achieved by reducing the critical areas where the circuit failures are likely to happen. This gridless area router bene... A new gridless router to improve the yield of IC layout is presented. The improvement of yield is achieved by reducing the critical areas where the circuit failures are likely to happen. This gridless area router benefits from a novel cost function to compute critical areas during routing process, and heuristically lays the patterns on the chip area where it is less possible to induce critical area. The router also takes other objectives into consideration, such as routing completion rate and nets length. It takes advantage of gridless routing to gain more flexibility and a higher completion rate. The experimental results show that critical areas are effectively decreased by 21% on average while maintaining the routing completion rate over 99%. 展开更多
关键词 design for yield critical area gridless routing integrated circuit layout
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