Research of the test generation algorithm based on search state dominance for combinational circuit

On the basis of EST (Equivalent STate hashing) algorithm, this paper researches a kind of test generation algorithm based on search state dominance for combinational circuit. According to the dominance relation of the E-frontier (evaluation frontier), we can prove that this algorithm can terminate unnecessary searching step of test pattern earlier than the EST algorithm through some examples, so this algorithm can reduce the time of test generation. The test patterns calculated can detect faults given through simulation.

The structure-based multi-fault test generation algorithm for combinational circuit

In this paper the structure-based test generation algorithm has been studied for the problem that test patterns are obtained by determined finite faults set in the past. This Algorithm can find out all test patterns one tithe, so faults detection is very convenient. By simulation, the smallest test patterns set can be obtained and faults coverage rate is 100%.

A new approach to test generation for combinational circuits

Aimed at the generation of high-quality test set in the shortest possible time, the test generation for combinational circuits （CC） based on the chaotic particle swarm optimization （CPSO） algorithm is presented according to the analysis of existent problems of CC test generation, and an appropriate CPSO algorithm model has been constructed. With the help of fault simulator, the test set of ISCAS＇ 85 benchmark CC is generated using the CPSO, and some techniques are introduced such as half-random generation, and simulation of undetected fauhs.with original test vector, and inverse test vector. Experimental results show that this algorithm can generate the same fault coverage and small-size test set in short time compared with other known similar methods, which proves that the proposed method is applicable and effective.

Test Generation and Design-for-Testability Based on Acyclic Structure with Hold Registers

We present a method of test generation for acyclic sequential circuits with hold registers. A complete (100% fault efficiency) test sequence for an acyclic sequential circuit can be obtained by applying a combinational test generator to all the maximal time-expansion models (TEMs) of the circuit. We propose a class of acyclic sequential circuits for which the number of maximal TEMs is one, i.e, the maximum TEM exists. For a circuit in the class, test generation can be performed by using only the maximum TEM. The proposed class of sequential circuits with the maximum TEM properly includes several known classes of acyclic sequential circuits such as balanced structures and acyclic sequential circuits without hold registers for which test generation can be also performed by using a combinational test generator. Therefore, in general, the hardware overhead for partial scan based on the proposed structure is smaller than that based on balanced or acyclic sequential structure without hold registers.

Pseudo-Random Test Generation for Large Combinational Circuits

In this paper,a simulation system of pseudo-random testing is described first to investigate the characteristics of pseudo-random testing.Several interesting experimental results are obtained.It is found out that initial states of pseudo-random sequences have little effect on fault coverage.Fixed connection between LFSR outputs and circuit inputs in which the number of LFSR stages m is less than the number of circuit inputs n leads to low fault coverage,and the fault coverage is reduced as m decreases.The local unrandomness of pseudo-random sequences is exposed clearly.Generally,when an LFSR is employed as a pseudo-random generator,there are at least as many LFSR stages as circuit inputs.However,for large circuits under test with hundreds of inputs,there are drawbacks of using an LFSR with hundreds of stages.In the paper,a new design for a pseudo-random pattern generator is proposed in which m<n.The relationship between test length and the number of LFSR stages is discussed in order to obtain necessary,fault coverage.It is shown that the design cannot only save LFSR hardware but also reduce test length without loss of fault coverage,and is easy to implement. The experimental results are provided for the 10 Benchmark Circuits to show the effectiveness of the generator.

A Complete Critical Path Algorithm for Test Generation of Combinational Circuits

It is known that critical path test generation method is not a complete algorithm for combinational circuits with reconvergent-fanout.In order to make it a complete algorithm,we put forward a reconvergent-fanout- oriented technique,the principal critical path algorithm,propagating the critical value back to primary inputs along a single path,the principal critical path,and allowing multiple path sensitization if needed.Relationship among test patterns is also discussed to accelerate test generation.

Test system of the front-end readout for an application-specific integrated circuit for the water Cherenkov detector array at the large high-altitude air shower observatory

The water Cherenkov detector array(WCDA) is an important part of the large high-altitude air shower observatory(LHAASO),which is in a research and development phase.The central scientific goal of LHAASO is to explore the origin of high-energy cosmic rays of the universe and to push forward the frontier of new physics.To simplify the WCDA's readout electronics,a prototype of a front-end readout for an application-specific integrated circuit(ASIC) is designed based on the timeover-threshold method to achieve charge-to-time conversion.High-precision time measurement and charge measurement are necessary over a full dynamic range[1-4000photoelectrons(P.E.)].To evaluate the performance of this ASIC,a test system is designed that includes the front-end ASIC test module,digitization module,and test software.The first module needs to be customized for different ASIC versions,whereas the digitization module and test software are tested for general-purpose use.In the digitization module,a field programmable gate array-based time-todigital converter is designed with a bin size of 333 ps,which also integrates an inter-integrated circuit to configure the ASIC test module,and a universal serial bus interface is designed to transfer data to the remote computer.Test results indicate that the time resolution is better than 0.5 ns,and the charge resolution is better than 30%root mean square(RMS) at 1 P.E.and 3%RMS at 4000 P.E.,which are beyond the application requirements.

Influence of Tilted Angle on Effective Linear Energy Transfer in Single Event Effect Tests for Integrated Circuits at 130 nm Technology Node

A heavy-ion irradiation experiment is studied in digital storage cells with different design approaches in 130？nm CMOS bulk Si and silicon-on-insulator （SOI） technologies. The effectiveness of linear energy transfer （LET） with a tilted ion beam at the 130？nm technology node is obtained. Tests of tilted angles θ=0 ° , 30 ° and 60 ° with respect to the normal direction are performed under heavy-ion Kr with certain power whose LET is about 40？MeVcm 2 /mg at normal incidence. Error numbers in D flip-flop chains are used to determine their upset sensitivity at different incidence angles. It is indicated that the effective LETs for SOI and bulk Si are not exactly in inverse proportion to cosθ , furthermore the effective LET for SOI is more closely in inverse proportion to cosθ compared to bulk Si, which are also the well known behavior. It is interesting that, if we design the sample in the dual interlocked storage cell approach, the effective LET in bulk Si will look like inversely proportional to cosθ very well, which is also specifically explained.

Predicting stability of integrated circuit test equipment using upper side boundary values of normal distribution

In response to the growing complexity and performance of integrated circuit(IC),there is an urgent need to enhance the testing and stability of IC test equipment.A method was proposed to predict equipment stability using the upper side boundary value of normal distribution.Initially,the K-means clustering algorithm classifies and analyzes sample data.The accuracy of this boundary value is compared under two common confidence levels to select the optimal threshold.A range is then defined to categorize unqualified test data.Through experimental verification,the method achieves the purpose of measuring the stability of qualitative IC equipment through a deterministic threshold value and judging the stability of the equipment by comparing the number of unqualified data with the threshold value,which realizes the goal of long-term operation monitoring and stability analysis of IC test equipment.

An optimal stacking order for mid-bond testing cost reduction of 3D IC

In order to solve the problem that the testing cost of the three-dimensional integrated circuit(3D IC)is too high,an optimal stacking order scheme is proposed to reduce the mid-bond test cost.A new testing model is built with the general consideration of both the test time for automatic test equipment(ATE)and manufacturing failure factors.An algorithm for testing cost and testing order optimization is proposed,and the minimum testing cost and optimized stacking order can be carried out by taking testing bandwidth and testing power as constraints.To prove the influence of the optimal stacking order on testing costs,two baselines stacked in sequential either in pyramid type or in inverted pyramid type are compared.Based on the benchmarks from ITC 02,experimental results show that for a 5-layer 3D IC,under different constraints,the optimal stacking order can reduce the test costs on average by 13%and 62%,respectively,compared to the pyramid type and inverted pyramid type.Furthermore,with the increase of the stack size,the test costs of the optimized stack order can be decreased.

TEST OF BOARD-LEVEL BOUNDARY SCAN INTEGRITY

The IEEE Standard 1149.1 boundary scan (BS) implementation provides the internal access required for testing the digital printed circuit board (PCB). However, the integrity of the boundary scan test infrastructure should be tested first to guarantee the validation of the results of the rest functional test and diagnosis. This paper describes the fault models and test principles of the BS test access port (TAP) lines on PCBs. A test algorithm with high fault coverage and short time is then presented for the PCB on which all ICs are BS ones.

集成电路测试新工科人才产教融合培养模式探索与实践

集成电路测试是集成电路设计制造产业中的重要环节。针对目前国内集成电路测试行业专门技术人才紧缺的现实需求,合肥工业大学联合国内外集成电路产业知名企业,从课程教学内容与教学方法、实验平台建设与实验设计、创新能力培养与学科竞赛等环节入手,在仪器类专业探索现阶段适合于集成电路测试新工科人才培养的校企合作办学模式。近年来,在集成电路测试课程体系完善、实验平台建设、实践环节培养等方面均取得较好的成果,为新工科人才产教融合培养提供实践经验和参考案例。

集成电路测试管理系统的设计与实现

阐述在集成电路生产中的测试管理系统设计,该系统能够实现对测试数据的存储和管理,支持数据分析和测试报告的生成,提供测试参数配置和测试流程管理功能。

塑封集成电路HAST影响因素探讨

随着塑封集成电路在人工智能、移动互联网、物联网、云计算和大数据等领域的广泛应用,其面临长时间加电连续工作的需求,因此需要对其长期可靠性进行研究。结合试验实例,分别从设备、试验硬件和导线材质等方面对塑封集成电路高加速应力试验(HAST)的影响因素进行了分析。分析结果表明采用高纯水、优化温湿度控制程序可避免凝露引发的集成电路试验过程失效;导电性阳极丝(CAF)和电化学迁移(ECM)是HAST中常见失效问题,试验硬件与工艺需做好CAF和ECM防控;试验线材会影响HAST,线材绝缘层与线芯材质要定期监测,适时更换。

新型IGCT直流输电换流阀运行试验研究及其等效性评估

换相失败问题(commutation failure,CF)是电网换相换流高压直流输电技术(line commutated converter high voltage directcurrent,LCC-HVDC)面临的固有难题。为了解决该问题,已有文献主要从拓扑结构、控制策略等方面着手,鲜见抵御换相失败的新型换流阀研制及试验研究。该文开展基于大功率逆阻型集成门极换流晶闸管(reverse blocking integrated gate commutated thyristor,RB-IGCT)的新型换流阀试验研究及试验等效性分析。首先,阐释新型换流阀抵御换相失败的原理,并针对新型换流阀不同的工作模式,提出对新型电力电子器件的需求。然后,利用现有的型式试验合成回路平台开展适用于传统晶闸管换流阀的运行试验,并分析试验结果,得出大部分试验项目等效性较好而小熄弧角试验和关断试验等效性较差的结论。最后,针对这两项特殊试验提出新的试验方法和试验电路,可为新型换流阀的研发和应用提供一定的技术基础。

基于ATE的高速DAC射频参数SFDR测试技术优化

利用集成电路自动测试设备(ATE)测试高速DAC射频参数时,由于ATE测试板PCB走线较长、损耗较大以及机台提供的信号抖动比实装大等原因,导致ATE上高速DAC射频参数测试指标低于实装测试值。为此,文中介绍DAC电路的工作原理和测试方法;其次为解决上述问题,对测试码的生成以及PCB的布局等进行一系列改进,并将改进前后的测试值与典型值进行对比。结果表明,改进措施成效显著,大大优化了高速DAC射频参数的测试指标,使得SFDR等高频DAC动态类参数指标接近或达到实装测试值。

核电厂一回路计算机压力控制系统的研发与应用

核电机组一回路是核电厂的第二道安全屏障,其可靠性和严密性对于核电安全至关重要。我国几乎所有核电机组进行一回路承压能力和密封测试的压力控制均为手动操作,控制精度低、劳动强度大、压力读数误差大,存在很大的人因失效风险。针对该问题,研发了一套计算机控制系统来实现水压试验的自动控制,阐述了该计算机控制系统软、硬件系统设计和实现方案,并介绍了人机交互界面的功能要素和实现形式。结果表明,该系统能很好地完成一回路水压试验过程的自动控制任务。

基于功率MOS管的板级干扰器设计

为了解决集成电路抗扰性测试设备占据空间大、存在外部电路元件击穿等安全隐患问题,提出了一种可以对集成电路芯片源端电压进行周期性扰动的板级干扰器。该干扰器以低阻抗MOS管与肖特基二极管串联结构作为输出驱动,通过FPGA来周期性控制MOS管开关,根据相位累加的原理合成出干扰电源信号,且能通过改变FPGA输出频率和反馈电阻大小来实现干扰电源信号频率与幅度的调节。将干扰器接入负载电路进行测试,结果表明:干扰器在1 MHz~10 MHz与60 MHz~100 MHz频段,对3Ω,50 pF负载的电源端扰动幅值达到0.6 V以上,驱动能力理想。因此该干扰器适合作为干扰信号源应用于实际的芯片电源端在1 MHz~10 MHz与60 MHz~100 MHz频段的电磁干扰测试实验;相比较于现有的设备,其具有结构简单、低功耗、大驱动、成本低、安全方便等优点。

集成电路测试行业现状分析及建议

集成电路测试是集成电路产业链中不可或缺的环节,集成电路测试能够有效保障产品的质量和性能,目前国内集成电路测试行业发展迅猛,但是和国外相比仍有一定差距。本文分析当前集成电路测试行业现状及发展趋势,剖析集成电路测试行业存在的问题。当前集成电路测试行业市场集中度、资源利用率、行业透明度均不高,缺少高端人才,行业内企业的融资能力较弱。针对存在的问题提出相应建议,加强测试能力的规划布局、加快关键测试能力的建设、培育和增强核心竞争力、创新行业人才培养模式和加大财税金融支持力度。

基于片上时钟控制器的电路全速测试设计与实现

阐述芯片在55nm CMOS工艺下,基于片上时钟控制器,对电路的数字逻辑部分、嵌入式存储器部分分别进行全速测试的可测性设计。通过对芯片全速测试的可测性设计和验证,测试时间得到缩短。