INTEGRATED LAYOUT DESIGN OF CELLS AND FLOW PATHS

The integrated layout problem in manufacturing Systems is investigated. Anintegrated model for Concurrent layout design of cells and flow paths is formulated. A hybridapproach combined an enhanced branch-and-bound algorithm with a simulated annealing scheme isproposed to solve this problem. The integrated layout method is applied to re-layout the gear pumpshop of a medium-size manufacturer of hydraulic pieces. Results show that the proposed layout methodcan concurrently provide good solutions of the cell layouts and the flow path layouts.

Integrated Layout and Transfer of Urban Rail Transit Hubs

This paper is engaged in the research of urban rail transit hub integration and transfer.Firstly,this paper focuses on the space division,the aggregation form of hub subsystems,the spatial layout of hub subsystems,and the design of integrated functions to achieve an integrated layout.In addition,this study also conducted a selection of transfer classification and transfer station layout of urban rail transit hubs,with the aims to promote the improvement of the functions of urban rail transit hubs,the rationality of transfers,and to improve the service quality of the hub system which meet the demand of the public travel.

Low phase noise LC VCO design in CMOS technology

This paper presents the design and the experimental measurements of two complementary metal-oxide-semiconductor (CMOS) LC-tuned voltage controlled oscillators (VCO) implemented in a 0.18 μm 6-metal-layer mixed-signal/RF CMOS technology. The design methodologies and approaches for the optimization of the ICs are presented. The first design is optimized for mixed-signal transistor, oscillated at 2.64 GHz with a phase noise of -93.5 dBc/Hz at 500 kHz offset. The second one optimized for RF transistor, using the same architecture, oscillated at 2.61 GHz with a phase noise of -95.8 dBc/Hz at 500 kHz offset. Under a 2 V supply, the power dissipation is 8 mW, and the maximum buffered output power for mixed-signal and RF transistor are -7 dBm and -5.4 dBm, respectively. Both kinds of oscillators make use of on-chip components only, allowing for simple and robust integration.

Analog Module Placement Design Using Genetic Algorithm

This paper presents a novel genetic algorithm for analog module placement based on a generalization of the two-dimensional bin packing problem. The genetic encoding and operators assure that all problem constraints are always satisfied. Thus the potential problems of adding penalty terms to the cost function are eliminated so that the search configuration space is drastically decreased. The dedicated cost function is based on the special requirements of analog integrated circuits. A fractional factorial experiment was conducted using an orthogonal array to study the algorithm parameters. A meta-GA was applied to determine the optimal parameter values. The algorithm was tested with several local benchmark circuits. The experimental results show that the algorithm has better performance than the simulated annealing approach with satisfactory results comparable to manual placement. This study demonstrates the effectiveness of the genetic algorithm in the analog module placement problem. The algorithm has been successfully used in a layout synthesis tool.

A Yield-Driven Gridless Router

A new gridless router to improve the yield of IC layout is presented. The improvement of yield is achieved by reducing the critical areas where the circuit failures are likely to happen. This gridless area router benefits from a novel cost function to compute critical areas during routing process, and heuristically lays the patterns on the chip area where it is less possible to induce critical area. The router also takes other objectives into consideration, such as routing completion rate and nets length. It takes advantage of gridless routing to gain more flexibility and a higher completion rate. The experimental results show that critical areas are effectively decreased by 21% on average while maintaining the routing completion rate over 99%.