Deep submicron process technology is widely being used and interconnect structures are becoming more and more complex.This means that the resistance calculation based on two-dimensional models can no longer provide su...Deep submicron process technology is widely being used and interconnect structures are becoming more and more complex.This means that the resistance calculation based on two-dimensional models can no longer provide sufficiently accurate results.This paper presents a three-dimensional resistance calculation method called the combined analytical formula and boundary element method(ABEM).The method cuts selected interconnecting lines then it calculates the resistances of straight sections using an analytical formula and the resistances of the other sections using the boundary element method(BEM).The resistances of the different sub-regions are combined to calculate the resistance of the entire region.Experiments on actual layouts show that compared with the commercial software Raphael based on finite difference method,the proposed method is 2-3 orders of magnitude faster.The ABEM method uses much less memory(about 0.1%-1%),and is more accurate than Raphael with default mesh partitions.The results illustrate that the proposed method is efficient and accurate.展开更多
Considering the self-heating effect, an accurate expression for the global interconnection resistance per unit length in terms of interconnection wire width and spacing is presented. Based on the proposed resistance m...Considering the self-heating effect, an accurate expression for the global interconnection resistance per unit length in terms of interconnection wire width and spacing is presented. Based on the proposed resistance model and according to the trade-off theory, a novel optimization analytical model of delay, power dissipation and bandwidth is derived. The proposed optimal model is verified and compared based on 90 nm, 65 nm and 40 nm CMOS technologies. It can be found that more optimum results can be easily obtained by the proposed model. This optimization model is more accurate and realistic than the conventional optimization models, and can be integrated into the global interconnection design ofnano-scale integrated circuits.展开更多
基金supported by National Science Foundation of China(No.90407004).
文摘Deep submicron process technology is widely being used and interconnect structures are becoming more and more complex.This means that the resistance calculation based on two-dimensional models can no longer provide sufficiently accurate results.This paper presents a three-dimensional resistance calculation method called the combined analytical formula and boundary element method(ABEM).The method cuts selected interconnecting lines then it calculates the resistances of straight sections using an analytical formula and the resistances of the other sections using the boundary element method(BEM).The resistances of the different sub-regions are combined to calculate the resistance of the entire region.Experiments on actual layouts show that compared with the commercial software Raphael based on finite difference method,the proposed method is 2-3 orders of magnitude faster.The ABEM method uses much less memory(about 0.1%-1%),and is more accurate than Raphael with default mesh partitions.The results illustrate that the proposed method is efficient and accurate.
基金supported by the National Natural Science Foundation of China(No.60606006)the Key Science&Technology Special Project of Shaanxi Province,China(No.2011KTCQ01-19)the National Defense Pre-Research Foundation of China(No.9140A23060111)
文摘Considering the self-heating effect, an accurate expression for the global interconnection resistance per unit length in terms of interconnection wire width and spacing is presented. Based on the proposed resistance model and according to the trade-off theory, a novel optimization analytical model of delay, power dissipation and bandwidth is derived. The proposed optimal model is verified and compared based on 90 nm, 65 nm and 40 nm CMOS technologies. It can be found that more optimum results can be easily obtained by the proposed model. This optimization model is more accurate and realistic than the conventional optimization models, and can be integrated into the global interconnection design ofnano-scale integrated circuits.
