Electric router is widely used for multi-core system to interconnect each other. However, with the increasing number of processor cores, the probability of communication conflict between processor cores increases, and...Electric router is widely used for multi-core system to interconnect each other. However, with the increasing number of processor cores, the probability of communication conflict between processor cores increases, and the data delay increases dramatically. With the advent of optical router, the traditional electrical interconnection mode has changed to optical interconnection mode. In the packet switched optical interconnection network, the data communication mechanism consists of 3 processes: link establishment, data transmission and link termination, but the circuit-switched data transmission method greatly limits the utilization of resources. The number of micro-ring resonators in the on-chip large-scale optical interconnect network is an important parameter affecting the insertion loss. The proposed λ-route, GWOR, Crossbar structure has a large overall network insertion loss due to the use of many micro-ring resonators. How to use the least micro-ring resonator to realize non-blocking communication between multiple cores has been a research hotspot. In order to improve bandwidth and reduce access latency, an optical interconnection structure called multilevel switching optical network on chip(MSONoC) is proposed in this paper. The broadband micro-ring resonators(BMRs) are employed to reduce the number of micro-ring resonators(MRs) in the network, and the structure can provide the service of non-blocking point to point communication with the wavelength division multiplexing(WDM) technology. The results show that compared to λ-route, GWOR, Crossbar and the new topology structure, the number of micro-ring resonators of MSONoC are reduced by 95.5%, 95.5%, 87.5%, and 60% respectively. The insertion loss of the minimum link of new topology, mesh and MSONoC structure is 0.73 dB, 0.725 dB and 0.38 dB.展开更多
An optical waveguide interconnect mesh network scheme for parallel multiprocessor systems based on an electro-optical printed circuit board （EOPCB） with multimode polymer waveguide is proposed. The system consists o...An optical waveguide interconnect mesh network scheme for parallel multiprocessor systems based on an electro-optical printed circuit board （EOPCB） with multimode polymer waveguide is proposed. The system consists of 2×2 processor element chips interconnected in a mesh network configuration. An additional layer with optical waveguide structure is embedded in a conventional printed circuit board to construct the EOPCB. Vertical cavity surface emitting laser （VCSEL）/positive intrinsic-negative （PIN） arrays are ap- plied as the optical transmitters/receivers. Three 1 ~ 12 VCSEL/PIN parallel optical transmitting/receiving modules are used to provide 32 input/output optical channels required by the 2~2 chip-to-chip optical mesh interconnect system. The data rate in each optical channel is 3.125 Gbps and thus 10 Gbps parallel optical interconnect link for each direction of a chip is obtained. The optical signals from a processor element chip can be transmitted to another chip through optical waveguide interconnect embedded in the board. Thus the optical interconnect mesh network for parallel multiprocessor system can be implemented.展开更多
The high-density server is featured as low power, low volume, and high computational density. With the rising use of high-density servers in data-intensive and large-scale web applications, it requires a high-performa...The high-density server is featured as low power, low volume, and high computational density. With the rising use of high-density servers in data-intensive and large-scale web applications, it requires a high-performance and cost-efficient intra-server interconnection network. Most of state-of-the-art high-density servers adopt the fully-connected intra-server network to attain high network performance. Unfortunately, this solution costs too much due to the high degree of nodes. In this paper, we exploit the theoretically optimized Moore graph to interconnect the chips within a server. Accounting for the suitable size of applications, a 50-size Moore graph, called Hoffman-Singleton graph, is adopted. In practice, multiple chips should be integrated onto one processor board, which means that the original graph should be partitioned into homogeneous connected subgraphs. However, the existing partition scheme does not consider above problem and thus generates heterogeneous subgraphs. To address this problem, we propose two equivalent-partition schemes for the Hoffman-Singleton graph. In addition, a logic-based and minimal routing mechanism, which is both time and area efficient, is proposed. Finally, we compare the proposed network architecture with its counterparts, namely the fully-connected, Kautz and Torus networks. The results show that our proposed network can achieve competitive performance as fully-connected network and cost close to Torus.展开更多
基金Supported by the National Natural Science Foundation of China(No.61834005,61772417,61802304,61602377,61634004)Shaanxi Provincial Co-ordination Innovation Project of Science and Technology(No.2016KTZDGY02-04-02)+1 种基金Shaanxi Provincial Key R&D Plan(No.2017GY-060)Shaanxi International Science and Technology Cooperation Program(No.2018KW-006).
文摘Electric router is widely used for multi-core system to interconnect each other. However, with the increasing number of processor cores, the probability of communication conflict between processor cores increases, and the data delay increases dramatically. With the advent of optical router, the traditional electrical interconnection mode has changed to optical interconnection mode. In the packet switched optical interconnection network, the data communication mechanism consists of 3 processes: link establishment, data transmission and link termination, but the circuit-switched data transmission method greatly limits the utilization of resources. The number of micro-ring resonators in the on-chip large-scale optical interconnect network is an important parameter affecting the insertion loss. The proposed λ-route, GWOR, Crossbar structure has a large overall network insertion loss due to the use of many micro-ring resonators. How to use the least micro-ring resonator to realize non-blocking communication between multiple cores has been a research hotspot. In order to improve bandwidth and reduce access latency, an optical interconnection structure called multilevel switching optical network on chip(MSONoC) is proposed in this paper. The broadband micro-ring resonators(BMRs) are employed to reduce the number of micro-ring resonators(MRs) in the network, and the structure can provide the service of non-blocking point to point communication with the wavelength division multiplexing(WDM) technology. The results show that compared to λ-route, GWOR, Crossbar and the new topology structure, the number of micro-ring resonators of MSONoC are reduced by 95.5%, 95.5%, 87.5%, and 60% respectively. The insertion loss of the minimum link of new topology, mesh and MSONoC structure is 0.73 dB, 0.725 dB and 0.38 dB.
基金supported by the National Natural Science Foundation of China(No.60677023)the National"863"Program of China(No.2006AA01Z240).
文摘An optical waveguide interconnect mesh network scheme for parallel multiprocessor systems based on an electro-optical printed circuit board （EOPCB） with multimode polymer waveguide is proposed. The system consists of 2×2 processor element chips interconnected in a mesh network configuration. An additional layer with optical waveguide structure is embedded in a conventional printed circuit board to construct the EOPCB. Vertical cavity surface emitting laser （VCSEL）/positive intrinsic-negative （PIN） arrays are ap- plied as the optical transmitters/receivers. Three 1 ~ 12 VCSEL/PIN parallel optical transmitting/receiving modules are used to provide 32 input/output optical channels required by the 2~2 chip-to-chip optical mesh interconnect system. The data rate in each optical channel is 3.125 Gbps and thus 10 Gbps parallel optical interconnect link for each direction of a chip is obtained. The optical signals from a processor element chip can be transmitted to another chip through optical waveguide interconnect embedded in the board. Thus the optical interconnect mesh network for parallel multiprocessor system can be implemented.
基金supported by the Strategic Priority Research Program of the Chinese Academy of Sciences under Grant No.XDA06010401the National Natural Science Foundation of China under Grant Nos.61202056,61331008,61221062the HuaweiResearch Program of China under Grant No.YBCB2011030
文摘The high-density server is featured as low power, low volume, and high computational density. With the rising use of high-density servers in data-intensive and large-scale web applications, it requires a high-performance and cost-efficient intra-server interconnection network. Most of state-of-the-art high-density servers adopt the fully-connected intra-server network to attain high network performance. Unfortunately, this solution costs too much due to the high degree of nodes. In this paper, we exploit the theoretically optimized Moore graph to interconnect the chips within a server. Accounting for the suitable size of applications, a 50-size Moore graph, called Hoffman-Singleton graph, is adopted. In practice, multiple chips should be integrated onto one processor board, which means that the original graph should be partitioned into homogeneous connected subgraphs. However, the existing partition scheme does not consider above problem and thus generates heterogeneous subgraphs. To address this problem, we propose two equivalent-partition schemes for the Hoffman-Singleton graph. In addition, a logic-based and minimal routing mechanism, which is both time and area efficient, is proposed. Finally, we compare the proposed network architecture with its counterparts, namely the fully-connected, Kautz and Torus networks. The results show that our proposed network can achieve competitive performance as fully-connected network and cost close to Torus.
