Effects of interface trap density on the electrical performance of amorphous InSnZnO thin-film transistor

We reported the influence of interface trap density（Nt） on the electrical properties of amorphous InSnZnO based thin-film transistors,which were fabricated at different direct-current（DC） magnetron sputtering powers.The device with the smallest Nt of 5.68×10^11 cm^-2 and low resistivity of 1.21×10^-3Ω·cm exhibited a turn-on voltage（V（ON）） of-3.60 V,a sub-threshold swing（S.S） of 0.16 V/dec and an on-off ratio（I（ON）/I（OFF）） of^8 x 10^8.With increasing Nt,the V（ON）,S.S and I（ON）/I（OFF） were suppressed to-9.40 V,0.24 V/dec and 2.59×10^8,respectively.The V（TH） shift under negative gate bias stress has also been estimated to investigate the electrical stability of the devices.The result showed that the reduction in Nt contributes to an improvement in the electrical properties and stability.

Research of Trap and Electron Density Distributions in the Interface of Polyimide/Al2O3 Nanocomposite Films Based on IDC and SAXS

The distributions of traps and electron density in the interfaces between polyimide （PI） matrix and Al2O3 nanoparticles are researched using the isothermal decay current and the small-angle x-ray scattering （SAXS） tests. According to the electron density distribution for quasi two-phase mixture doped by spherical nanoparticles, the electron densities in the interfaces of PI/Al2O3 nanocomposite films are evaluated. The trap level density and carrier mobility in the interface are studied. The experimental results show that the distribution and the change rate of the electron density in the three layers of interface are different, indicating different trap distributions in the interface layers. There is a maximum trap level density in the second layer, where the maximum trap level density for the nanocomposite film doped by 25 wt% is 1.054 × 10^22 eV·m^-3 at 1.324eV, resulting in the carrier mobility reducing. In addition, both the thickness and the electron density of the nanocomposite film interface increase with the addition of the doped Al2O3 contents. Through the study on the trap level distribution in the interface, it is possible to further analyze the insulation mechanism and to improve the performance of nano-dielectric materials.

Impact of nitrogen plasma passivation on the interface of germanium MOS capacitor

Nitrogen plasma passivation （NPP） on （111） germanium （Ge） was studied in terms of the interface trap density, roughness, and interfacial layer thickness using plasma-enhanced chemical vapor deposition （PECVD）. The results show that NPP not only reduces the interface states, but also improves the surface roughness of Ge, which is beneficial for suppressing the channel scattering at both low and high field regions of Ge MOSFETs. However, the interracial layer thickness is also increased by the NPP treatment, which will impact the equivalent oxide thickness （EOT） scaling and thus degrade the device performance gain from the improvement of the surface morphology and the interface passivation. To obtain better device performance of Ge MOSFETs, suppressing the interfacial layer regrowth as well as a trade-off with reducing the interface states and roughness should be considered carefully when using the NPP process.

High-Pressure Oxidation on Ge:Improvement of Ge/GeO2 Interface and GeO2 Bulk Properties

On the basis of thermodynamic and kinetic consideration of Ge-O system,high-pressure oxidation(HPO)on Ge was proposed to suppress the GeO desorption during the thermal oxidation and significant improvements of Ge/GeO2-based gate stacks have been achieved.It is found that the post oxidation annealing at lower temperatures is helpful to passivate the interface defects at the Ge/GeO2 stack generated by the conventional thermal oxidation,while the high-quality GeO2 bulk properties can only be achieved by HPO that grows GeO2 film at high temperatures without the GeO desorption.This paper reviews the advantage of HPO on the formation of Ge/GeO2 stacks in terms of Ge/GeO2 interface and GeO2 bulk properties.

Study on influences of TiN capping layer on time-dependent dielectric breakdown characteristic of ultra-thin EOT high-k metal gate NMOSFET with kMC TDDB simulations

The thickness effect of the TiN capping layer on the time dependent dielectric breakdown（TDDB） characteristic of ultra-thin EOT high-k metal gate NMOSFET is investigated in this paper.Based on experimental results,it is found that the device with a thicker TiN layer has a more promising reliability characteristic than that with a thinner TiN layer.From the charge pumping measurement and secondary ion mass spectroscopy（SIMS） analysis,it is indicated that the sample with the thicker TiN layer introduces more Cl passivation at the IL/Si interface and exhibits a lower interface trap density.In addition,the influences of interface and bulk trap density ratio Nit/Not are studied by TDDB simulations through combining percolation theory and the kinetic Monte Carlo（kMC） method.The lifetime reduction and Weibull slope lowering are explained by interface trap effects for TiN capping layers with different thicknesses.

Interfacial and electrical characteristics of a HfO_2/n–InAlAs MOS-capacitor with different dielectric thicknesses

AHfO2/n–In Al As MOS-capacitor has the advantage of reducing the serious gate leakage current when it is adopted in In As/Al Sb HEMT instead of the conventional Schottky-gate. In this paper, three kinds of Hf O2/n–InAlAs MOS-capacitor samples with different Hf O2 thickness values of 6, 8, and 10 nm are fabricated and used to investigate the interfacial and electrical characteristics. As the thickness is increased, the equivalent dielectric constant ε ox of Hf O2 layer is enhanced and the In AlAsHfO2 interface trap density Ditis reduced, leading to an effective reduction of the leakage current. It is found that the Hf O2 thickness of 10 nm is a suitable value to satisfy the demands of most applications of a HfO2/n–InAlAs MOS-capacitor, with a sufficiently low leakage current compromised with the threshold voltage.

Interfacial characteristics of Al/Al_2O_3/ZnO/n-GaAs MOS capacitor

The interfacial characteristics of Al/Al2O3/ZnO/n-GaAs metal-oxide-semiconductor （MOS） capacitor are investigated. The results measured by X-ray photoelectron spectroscopy （XPS） and high-resolution transmission electron microscopy （HRTEM） show that the presence of ZnO can effectively suppress the formations of oxides at the interface between the GaAs and gate dielectric and gain smooth interface. The ZnO-passivated GaAs MOS capacitor exhibits a very small hysteresis and frequency dispersion. Using the Terman method, the interface trap density is extracted from C-V curves. It is found that the ZnO layer can effectively improve the interface quality.

Hf-doped ZnO transistor with high bias stability and high field-effect mobility by modulation of oxygen vacancies and interfaces

ZnO-based thin film transistors(TFTs)with high bias stability are challenging due to the intrinsic defects and overhigh interface trap density.In this work,we fabricated Hf-doped ZnO films with different cycle ratio of Zn/Hf via atomic layer deposition and subsequent annealing treatment.The results show that the cycle ratio of Zn/Hf is optimized to be 10:1,and the corresponding atomic ratio is 2.24%.The threshold voltage and subthreshold swing of the devices are improved as the annealing temperature increases,owning to the decrease of the oxygen vacancies and interface trap density.Furthermore,we developed Hf-doped ZnO TFT with high bias stability by introducing HfO_(2)intermediate layer between the active layer and SiO_(2)dielectric layer,and the shift of threshold voltage is as low as-0.273 V,showing high bias stability.Also,the device has the high field-effective mobility of 52.4 cm^(2)/Vs,low subthreshold swing of 0.68 V/dec and high Ion/Ioff of 3.6×10^(8).The results indicate a promising fabrication method for highperformance ZnO-based TFTs,which may be applied in logic circuits,radio frequency identification and so on.

Effective interface passivation of a Ge/HfO_2 gate stack using ozone pre-gate treatment and ozone ambient annealing

The physical and electrical properties of a Ge/GeO2/HfO2/Al gate stack are investigated.A thin interfacial GeO2 layer（- 1 nm） is formed between Ge and HfO2 by dual ozone treatments,which passivates the Ge/high-k interface.Capacitors on p-type Ge substrates show very promising capacitance-voltage（C-V） characteristics by using in situ pre-gate ozone passivation and ozone ambient annealing after high-k deposition,indicating efficient passivation of the Ge/HfO2 interface.It is shown that the mid-gap interface state density at the Ge/GeO2 interface is 6.4×10^11 cm^-2·eV^-1.In addition,the gate leakage current density of the Ge/GeO2/HfO2/Al gate stack passivated by the dual ozone treatments is reduced by about three orders of magnitude compared to that of a Ge/HfO2/Al gate stack without interface passivation.