针对图像匹配中AKAZE(Accelerated-KAZE)算法匹配精度较低以及计算复杂等问题,提出了一种基于高斯滤波和AKAZE-LATCH(AKAZE-Learned Arrangements of Three Patch Codes)算法相融合的图像匹配算法。首先,对输入图像进行高斯滤波预处理,...针对图像匹配中AKAZE(Accelerated-KAZE)算法匹配精度较低以及计算复杂等问题,提出了一种基于高斯滤波和AKAZE-LATCH(AKAZE-Learned Arrangements of Three Patch Codes)算法相融合的图像匹配算法。首先,对输入图像进行高斯滤波预处理,去除高斯噪声等连续性噪声,并且保留图像的边缘信息。然后通过LATCH算法为AKAZE算法构建高效的二进制描述子,再通过KNN(K Nearest Neighbors)算法得到对应的匹配对。最后结合USAC(Universal RANSAC)去除误匹配对方法进行再次筛选,得到最终的匹配结果。经实验对比,所设计的算法相较于AKAZE算法匹配精度更高,且具有良好的鲁棒性和可靠性,可用于多数复杂场景下的图像匹配。展开更多
With the development of semiconductor technology,the size of transistors continues to shrink.In complex radiation environments in aerospace and other fields,small-sized circuits are more prone to soft error(SE).Curren...With the development of semiconductor technology,the size of transistors continues to shrink.In complex radiation environments in aerospace and other fields,small-sized circuits are more prone to soft error(SE).Currently,single-node upset(SNU),double-node upset(DNU)and triple-node upset(TNU)caused by SE are relatively common.TNU’s solution is not yet fully mature.A novel and low-cost TNU self-recoverable latch(named NLCTNURL)was designed which is resistant to harsh radiation effects.When analyzing circuit resiliency,a double-exponential current source is used to simulate the flipping behavior of a node’s stored value when an error occurs.Simulation results show that the latch has full TNU self-recovery.A comparative analysis was conducted on seven latches related to TNU.Besides,a comprehensive index combining delay,power,area and self-recovery—DPAN index was proposed,and all eight types of latches from the perspectives of delay,power,area,and DPAN index were analyzed and compared.The simulation results show that compared with the latches LCTNURL and TNURL which can also achieve TNU self-recoverable,NLCTNURL is reduced by 68.23%and 57.46%respectively from the perspective of delay.From the perspective of power,NLCTNURL is reduced by 72.84%and 74.19%,respectively.From the area perspective,NLCTNURL is reduced by about 28.57%and 53.13%,respectively.From the DPAN index perspective,NLCTNURL is reduced by about 93.12%and 97.31%.The simulation results show that the delay and power stability of the circuit are very high no matter in different temperatures or operating voltages.展开更多
By using the pulsed laser single event effect facility and electro-static discharge （ESD） test system, the characteristics of the ＂high current＂, relation with external stimulus and relevance to impacted modes of ...By using the pulsed laser single event effect facility and electro-static discharge （ESD） test system, the characteristics of the ＂high current＂, relation with external stimulus and relevance to impacted modes of single event latch-up （SEL） and transient-induced latch-up （TLU） are studied, respectively, for a 12-bit complementary metal--oxide semiconductor （CMOS） analog-to-digital converter. Furthermore, the sameness and difference in physical mechanism between ＂high current＂ induced by SEL and that by TLU are disclosed in this paper. The results show that the minority carrier diffusion in the PNPN structure of the CMOS device which initiates the active parasitic NPN and PNP transistors is the common reason for the ＂high current＂ induced by SEL and for that by TLU, However, for SEL, the minority carder diffusion is induced by the ionizing radiation, and an underdamped sinusoidal voltage on the supply node （the ground node） is the cause of the minority carrier diffusion for TLU.展开更多
The current research of nuclear control rod drive mechanism(CRDM)movable latch only makes a simple measurement of wear mass.The wear volume and difference in various claw surfaces are ignored and the degradation mecha...The current research of nuclear control rod drive mechanism(CRDM)movable latch only makes a simple measurement of wear mass.The wear volume and difference in various claw surfaces are ignored and the degradation mechanism of each claw surface is not clear.In this paper,a detailed degradation analysis was carried out on each claw surface of movable latch combined with wear result and worn morphology.Results indicate that the boundary of carbide is preferred for corrosion because carbide presents a nobler Volta potential compared to the metal matrix or boundary region.Due to the oscillation of drive shaft between the claw surfaces of movable latch,the dominant wear mechanism on the upper surface of claw(USC)and lower surface of claw(LSC)is plastic deformation caused by impact wear.Mechanical impact wear will cause the fragmentation of carbides because of the high hardness and low ductility of carbides.Corrosion promotes the broken carbides to fall off from the metal matrix.The generated fine carbides(abrasive particles)cause extra abrasive wear on USC when the movable brings the drive shaft upward or downward.As a result,USC has a higher wear volume than LSC.This research proposes a method to evaluate the wear on the whole movable latches using a 3D full-size scanner.展开更多
The latch-up effect induced by high-power microwave（HPM） in complementary metal–oxide–semiconductor（CMOS） inverter is investigated in simulation and theory in this paper. The physical mechanisms of excess carrie...The latch-up effect induced by high-power microwave（HPM） in complementary metal–oxide–semiconductor（CMOS） inverter is investigated in simulation and theory in this paper. The physical mechanisms of excess carrier injection and HPM-induced latch-up are proposed. Analysis on upset characteristic under pulsed wave reveals increasing susceptibility under shorter-width pulsed wave which satisfies experimental data, and the dependence of upset threshold on pulse repetitive frequency（PRF） is believed to be due to the accumulation of excess carriers. Moreover, the trend that HPMinduced latch-up is more likely to happen in shallow-well device is proposed.Finally, the process of self-recovery which is ever-reported in experiment with its correlation with supply voltage and power level is elaborated, and the conclusions are consistent with reported experimental results.展开更多
This paper reports on the performance evaluation of a novel latching-type electromagnetic actuator which is designed to be embedded at selected joints along single-port laparoscopic surgical instruments (SLS). The aim...This paper reports on the performance evaluation of a novel latching-type electromagnetic actuator which is designed to be embedded at selected joints along single-port laparoscopic surgical instruments (SLS). The aim of this actuator is to allow these instruments to become articulated with a push of a button in order to provide the optimum angulation required during SLS operations. This new actuator is comprised of electromagnetic coil elements, soft magnetic frames and a permanent magnet. Unlike conventional electromagnetic actuators, latching-type electromagnetic actuators could maintain their positions at either end of the actuation stroke without any power application requirement. In the current design, magnetic attraction forces initiated between the permanent magnet and the magnetic frame are utilised to lock the position of the actuator whilst a certain angulation position of the actuator is achieved as a result of the magnetic repulsion forces established between the permanent magnet and the coil elements. The performance of the new actuator in terms of the output force, maximum angulation and patient’s safety, was evaluated experimentally and the results were found to compare well with those acquired numerically using finite element methods. This actuator was seen to exhibit sufficient actuation forces and hence, it was capable of providing adaptable angulation characteristics for SLS tools. Finally, thermal evaluation of the actuator’s operation was conducted, which was found to be within safety limits specified by clinicians.展开更多
A new method of improving speed of latch-type comparators with preamplifier is presented. It investigates the relationship of current and transistor scales which affect delay time(tp) in latch. It applies a mathematic...A new method of improving speed of latch-type comparators with preamplifier is presented. It investigates the relationship of current and transistor scales which affect delay time(tp) in latch. It applies a mathematical model to optimize latch design. A figure of merit indicates that ratio Ipmos/Inmos is 0.25 in latch leading to optimal delay time. In order to suppress offset of latch, the cross-coupled loading, adopted in telescope preamplifier, which enhances the gain, is well analyzed and designed. The chip is fabricated in 0.18 μm CMOS technology. The delay time of latch comparator is less than 400 ps @500 MHz. The offset of comparator is estimated through Monte Carlo simulation. And power consumption is only 144 W under 1.8 V power supply. Results of on wafer testing are presented at the end of the paper. The chip occupies an area of 0.66×0.55 mm^2 and drains current of 80 μA.展开更多
The design of a new type of latching voltage comparator ZJ03 is described.Thecommon voltage comparators consist of multistage DC amplifiers,for which it is difficult to realizehigh speed and high precision.The ZJ03 co...The design of a new type of latching voltage comparator ZJ03 is described.Thecommon voltage comparators consist of multistage DC amplifiers,for which it is difficult to realizehigh speed and high precision.The ZJ03 comparator contains a controlled positive feedbackamplifier.Therefore,it is capable of realizing high speed and high precision.For improving theperformance and producibility,the tolerance extension,design centering and potential adaptingtechniques are used in the design of comparator ZJ03.展开更多
As technology scales down, clock distribution networks(CDNs) in integrated circuits(ICs) are becoming increasingly sensitive to single-event transients(SETs).The SET occurring in the CDN can even lead to failure of th...As technology scales down, clock distribution networks(CDNs) in integrated circuits(ICs) are becoming increasingly sensitive to single-event transients(SETs).The SET occurring in the CDN can even lead to failure of the entire circuit system. Understanding the factors that influence the SET sensitivity of the CDN is crucial to achieving radiation hardening of the CDN and realizing the design of highly reliable ICs. In this paper, the influences of different sequential elements(D-flip-flops and D-latches, the two most commonly used sequential elements in modern synchronous digital systems) on the SET susceptibility of the CDN were quantitatively studied. Electrical simulation and heavy ion experiment results reveal that the CDN-SET-induced incorrect latching is much more likely to occur in DFF and DFF-based designs. This can supply guidelines for the design of IC with high reliability.展开更多
文摘针对图像匹配中AKAZE(Accelerated-KAZE)算法匹配精度较低以及计算复杂等问题,提出了一种基于高斯滤波和AKAZE-LATCH(AKAZE-Learned Arrangements of Three Patch Codes)算法相融合的图像匹配算法。首先,对输入图像进行高斯滤波预处理,去除高斯噪声等连续性噪声,并且保留图像的边缘信息。然后通过LATCH算法为AKAZE算法构建高效的二进制描述子,再通过KNN(K Nearest Neighbors)算法得到对应的匹配对。最后结合USAC(Universal RANSAC)去除误匹配对方法进行再次筛选,得到最终的匹配结果。经实验对比,所设计的算法相较于AKAZE算法匹配精度更高,且具有良好的鲁棒性和可靠性,可用于多数复杂场景下的图像匹配。
基金The Open Project Program of the Shanxi Key Laboratory of Advanced Semiconductor Optoelectronic Devices and Integrated Systems(2023SZKF17)the University Synergy Innovation Program of Anhui Province(GXXT-2022-080)。
文摘With the development of semiconductor technology,the size of transistors continues to shrink.In complex radiation environments in aerospace and other fields,small-sized circuits are more prone to soft error(SE).Currently,single-node upset(SNU),double-node upset(DNU)and triple-node upset(TNU)caused by SE are relatively common.TNU’s solution is not yet fully mature.A novel and low-cost TNU self-recoverable latch(named NLCTNURL)was designed which is resistant to harsh radiation effects.When analyzing circuit resiliency,a double-exponential current source is used to simulate the flipping behavior of a node’s stored value when an error occurs.Simulation results show that the latch has full TNU self-recovery.A comparative analysis was conducted on seven latches related to TNU.Besides,a comprehensive index combining delay,power,area and self-recovery—DPAN index was proposed,and all eight types of latches from the perspectives of delay,power,area,and DPAN index were analyzed and compared.The simulation results show that compared with the latches LCTNURL and TNURL which can also achieve TNU self-recoverable,NLCTNURL is reduced by 68.23%and 57.46%respectively from the perspective of delay.From the perspective of power,NLCTNURL is reduced by 72.84%and 74.19%,respectively.From the area perspective,NLCTNURL is reduced by about 28.57%and 53.13%,respectively.From the DPAN index perspective,NLCTNURL is reduced by about 93.12%and 97.31%.The simulation results show that the delay and power stability of the circuit are very high no matter in different temperatures or operating voltages.
基金Project supported by the National Natural Science Foundation of China(Grant No.41304148)
文摘By using the pulsed laser single event effect facility and electro-static discharge （ESD） test system, the characteristics of the ＂high current＂, relation with external stimulus and relevance to impacted modes of single event latch-up （SEL） and transient-induced latch-up （TLU） are studied, respectively, for a 12-bit complementary metal--oxide semiconductor （CMOS） analog-to-digital converter. Furthermore, the sameness and difference in physical mechanism between ＂high current＂ induced by SEL and that by TLU are disclosed in this paper. The results show that the minority carrier diffusion in the PNPN structure of the CMOS device which initiates the active parasitic NPN and PNP transistors is the common reason for the ＂high current＂ induced by SEL and for that by TLU, However, for SEL, the minority carder diffusion is induced by the ionizing radiation, and an underdamped sinusoidal voltage on the supply node （the ground node） is the cause of the minority carrier diffusion for TLU.
基金Supported by Sichuan Science and Technology Program(Grant No.2019ZDZX0001)National Natural Science Foundation of China(Grant No.U2067221)Sichuan Science and Technology Planning Project(Grant No.22JCQN0111).
文摘The current research of nuclear control rod drive mechanism(CRDM)movable latch only makes a simple measurement of wear mass.The wear volume and difference in various claw surfaces are ignored and the degradation mechanism of each claw surface is not clear.In this paper,a detailed degradation analysis was carried out on each claw surface of movable latch combined with wear result and worn morphology.Results indicate that the boundary of carbide is preferred for corrosion because carbide presents a nobler Volta potential compared to the metal matrix or boundary region.Due to the oscillation of drive shaft between the claw surfaces of movable latch,the dominant wear mechanism on the upper surface of claw(USC)and lower surface of claw(LSC)is plastic deformation caused by impact wear.Mechanical impact wear will cause the fragmentation of carbides because of the high hardness and low ductility of carbides.Corrosion promotes the broken carbides to fall off from the metal matrix.The generated fine carbides(abrasive particles)cause extra abrasive wear on USC when the movable brings the drive shaft upward or downward.As a result,USC has a higher wear volume than LSC.This research proposes a method to evaluate the wear on the whole movable latches using a 3D full-size scanner.
基金Project supported by the Open Fund of Key Laboratory of Complex Electromagnetic Environment Science and Technology,China Academy of Engineering Physics(Grant No.2015-0214.XY.K)
文摘The latch-up effect induced by high-power microwave（HPM） in complementary metal–oxide–semiconductor（CMOS） inverter is investigated in simulation and theory in this paper. The physical mechanisms of excess carrier injection and HPM-induced latch-up are proposed. Analysis on upset characteristic under pulsed wave reveals increasing susceptibility under shorter-width pulsed wave which satisfies experimental data, and the dependence of upset threshold on pulse repetitive frequency（PRF） is believed to be due to the accumulation of excess carriers. Moreover, the trend that HPMinduced latch-up is more likely to happen in shallow-well device is proposed.Finally, the process of self-recovery which is ever-reported in experiment with its correlation with supply voltage and power level is elaborated, and the conclusions are consistent with reported experimental results.
文摘This paper reports on the performance evaluation of a novel latching-type electromagnetic actuator which is designed to be embedded at selected joints along single-port laparoscopic surgical instruments (SLS). The aim of this actuator is to allow these instruments to become articulated with a push of a button in order to provide the optimum angulation required during SLS operations. This new actuator is comprised of electromagnetic coil elements, soft magnetic frames and a permanent magnet. Unlike conventional electromagnetic actuators, latching-type electromagnetic actuators could maintain their positions at either end of the actuation stroke without any power application requirement. In the current design, magnetic attraction forces initiated between the permanent magnet and the magnetic frame are utilised to lock the position of the actuator whilst a certain angulation position of the actuator is achieved as a result of the magnetic repulsion forces established between the permanent magnet and the coil elements. The performance of the new actuator in terms of the output force, maximum angulation and patient’s safety, was evaluated experimentally and the results were found to compare well with those acquired numerically using finite element methods. This actuator was seen to exhibit sufficient actuation forces and hence, it was capable of providing adaptable angulation characteristics for SLS tools. Finally, thermal evaluation of the actuator’s operation was conducted, which was found to be within safety limits specified by clinicians.
基金Supported by the National Nature Science Foundation of China(No.61674037)the National Key Research and Development Program(No.2016YFC0800400)the Priority Academic Program Development of Jiangsu Higher Education Institutions
文摘A new method of improving speed of latch-type comparators with preamplifier is presented. It investigates the relationship of current and transistor scales which affect delay time(tp) in latch. It applies a mathematical model to optimize latch design. A figure of merit indicates that ratio Ipmos/Inmos is 0.25 in latch leading to optimal delay time. In order to suppress offset of latch, the cross-coupled loading, adopted in telescope preamplifier, which enhances the gain, is well analyzed and designed. The chip is fabricated in 0.18 μm CMOS technology. The delay time of latch comparator is less than 400 ps @500 MHz. The offset of comparator is estimated through Monte Carlo simulation. And power consumption is only 144 W under 1.8 V power supply. Results of on wafer testing are presented at the end of the paper. The chip occupies an area of 0.66×0.55 mm^2 and drains current of 80 μA.
文摘The design of a new type of latching voltage comparator ZJ03 is described.Thecommon voltage comparators consist of multistage DC amplifiers,for which it is difficult to realizehigh speed and high precision.The ZJ03 comparator contains a controlled positive feedbackamplifier.Therefore,it is capable of realizing high speed and high precision.For improving theperformance and producibility,the tolerance extension,design centering and potential adaptingtechniques are used in the design of comparator ZJ03.
基金supported by the National Natural Science Foundation of China(No.61434007)the National Natural Science Foundation of China(No.61704192)
文摘As technology scales down, clock distribution networks(CDNs) in integrated circuits(ICs) are becoming increasingly sensitive to single-event transients(SETs).The SET occurring in the CDN can even lead to failure of the entire circuit system. Understanding the factors that influence the SET sensitivity of the CDN is crucial to achieving radiation hardening of the CDN and realizing the design of highly reliable ICs. In this paper, the influences of different sequential elements(D-flip-flops and D-latches, the two most commonly used sequential elements in modern synchronous digital systems) on the SET susceptibility of the CDN were quantitatively studied. Electrical simulation and heavy ion experiment results reveal that the CDN-SET-induced incorrect latching is much more likely to occur in DFF and DFF-based designs. This can supply guidelines for the design of IC with high reliability.
