提出了1种基于0.18μm CMOS工艺的低压低功耗、宽锁定范围、低复杂度的2分频直接注入锁定分频器.该分频器采用Class-C的LC-tank架构来降低电源电压,同时改善LC振荡器的起振情况.此外还采用双端注入混频技术来扩大锁定范围.仿真结果表明...提出了1种基于0.18μm CMOS工艺的低压低功耗、宽锁定范围、低复杂度的2分频直接注入锁定分频器.该分频器采用Class-C的LC-tank架构来降低电源电压,同时改善LC振荡器的起振情况.此外还采用双端注入混频技术来扩大锁定范围.仿真结果表明该分频器有很好的混频性能,且分频器核心电路(不包括输出buffer)在800 m V电源电压下的功耗仅为0.91 m W.在注入信号的功率为0 d Bm时,该分频器在没有任何调谐单元时的锁定范围为6.4-8.5 GHz.展开更多
This paper proposes CMOS LC-tank divide-by-3 injection locked frequency dividers(ILFDs)fabricated in 0.18μn and 90nm CMOS process and describes the circuit design,operation principle and measurement results of the IL...This paper proposes CMOS LC-tank divide-by-3 injection locked frequency dividers(ILFDs)fabricated in 0.18μn and 90nm CMOS process and describes the circuit design,operation principle and measurement results of the ILFDs.The ILFDs use two injection series-MOSFETs across the LC resonator and a differential injection signal is applied to the gates of injection MOSFETs.The direct-injection divide-by-3 ILFDs are potential for radio-frequency application and can have wide locking range.展开更多
This paper presents a new design of complementary oxide semiconductor voltage controlled oscillator (CMOS VCO) for improve tuning range and phase noise with low power consumption. Design is area efficient and easy to ...This paper presents a new design of complementary oxide semiconductor voltage controlled oscillator (CMOS VCO) for improve tuning range and phase noise with low power consumption. Design is area efficient and easy to implement. Design is carried out in cadence and schematic editor using 180 nm technology. Simulation is done and performance results are reported. Results have been compared with earlier published work and improvements are obtained in this work.展开更多
建立了差分互补型电感电容压控振荡器(LC-VCO)的等效分析模型。采用有效截止频率fT,eff来表征MOS管的充放电能力,结合振荡器起振后共模输出电压下降的现象,提出了优化1/f3相位噪声的方法。采用该方法并结合跨导效率gm/ID设计方法,实现了...建立了差分互补型电感电容压控振荡器(LC-VCO)的等效分析模型。采用有效截止频率fT,eff来表征MOS管的充放电能力,结合振荡器起振后共模输出电压下降的现象,提出了优化1/f3相位噪声的方法。采用该方法并结合跨导效率gm/ID设计方法,实现了LC-VCO 1/f3相位噪声的优化,并在0.18μm CMOS工艺上获得验证。结果表明,该优化方法可以使频偏在1 k Hz以内的相位噪声改善2~3 d B,可用于开环LC-VCO作为本振的低功耗无线收发机及高性能晶体振荡器的电路设计中。展开更多
A 50 GHz cross-coupled voltage controlled oscillator（VCO） considering the coupling effect of inductors based on a 65 nm standard complementary metal oxide semiconductor（CMOS） technology is reported.A pair of induc...A 50 GHz cross-coupled voltage controlled oscillator（VCO） considering the coupling effect of inductors based on a 65 nm standard complementary metal oxide semiconductor（CMOS） technology is reported.A pair of inductors has been fabricated,measured and analyzed to characterize the coupling effects of adjacent inductors. The results are then implemented to accurately evaluate the VCO＇s LC tank.By optimizing the tank voltage swing and the buffer＇s operation region,the VCO achieves a maximum efficiency of 11.4%by generating an average output power of 2.5 dBm while only consuming 19.7 mW（including buffers）.The VCO exhibits a phase noise of-87 dBc/Hz at 1 MHz offset,leading to a figure of merit（FoM） of-167.5 dB/Hz and a tuning range of 3.8%（from 48.98 to 50.88 GHz）.展开更多
This paper discusses the design of a fully differential 2.1 GHz CMOS low noise amplifier using the TSMC 0.25 μm CMOS process. Intended for use in 3G, the low noise amplifier is fully integrated and without off-chip c...This paper discusses the design of a fully differential 2.1 GHz CMOS low noise amplifier using the TSMC 0.25 μm CMOS process. Intended for use in 3G, the low noise amplifier is fully integrated and without off-chip components. The design uses an LC tank to replace a large inductor to achieve a smaller die area, and uses shielded pad capacitances to improve the noise performance. This paper also presents evaluation results of the design.展开更多
文摘提出了1种基于0.18μm CMOS工艺的低压低功耗、宽锁定范围、低复杂度的2分频直接注入锁定分频器.该分频器采用Class-C的LC-tank架构来降低电源电压,同时改善LC振荡器的起振情况.此外还采用双端注入混频技术来扩大锁定范围.仿真结果表明该分频器有很好的混频性能,且分频器核心电路(不包括输出buffer)在800 m V电源电压下的功耗仅为0.91 m W.在注入信号的功率为0 d Bm时,该分频器在没有任何调谐单元时的锁定范围为6.4-8.5 GHz.
文摘This paper proposes CMOS LC-tank divide-by-3 injection locked frequency dividers(ILFDs)fabricated in 0.18μn and 90nm CMOS process and describes the circuit design,operation principle and measurement results of the ILFDs.The ILFDs use two injection series-MOSFETs across the LC resonator and a differential injection signal is applied to the gates of injection MOSFETs.The direct-injection divide-by-3 ILFDs are potential for radio-frequency application and can have wide locking range.
文摘This paper presents a new design of complementary oxide semiconductor voltage controlled oscillator (CMOS VCO) for improve tuning range and phase noise with low power consumption. Design is area efficient and easy to implement. Design is carried out in cadence and schematic editor using 180 nm technology. Simulation is done and performance results are reported. Results have been compared with earlier published work and improvements are obtained in this work.
文摘建立了差分互补型电感电容压控振荡器(LC-VCO)的等效分析模型。采用有效截止频率fT,eff来表征MOS管的充放电能力,结合振荡器起振后共模输出电压下降的现象,提出了优化1/f3相位噪声的方法。采用该方法并结合跨导效率gm/ID设计方法,实现了LC-VCO 1/f3相位噪声的优化,并在0.18μm CMOS工艺上获得验证。结果表明,该优化方法可以使频偏在1 k Hz以内的相位噪声改善2~3 d B,可用于开环LC-VCO作为本振的低功耗无线收发机及高性能晶体振荡器的电路设计中。
基金Project supported by the Special Fund on IOT Technology Research from China Government(No.YORSKB 1001)
文摘A 50 GHz cross-coupled voltage controlled oscillator（VCO） considering the coupling effect of inductors based on a 65 nm standard complementary metal oxide semiconductor（CMOS） technology is reported.A pair of inductors has been fabricated,measured and analyzed to characterize the coupling effects of adjacent inductors. The results are then implemented to accurately evaluate the VCO＇s LC tank.By optimizing the tank voltage swing and the buffer＇s operation region,the VCO achieves a maximum efficiency of 11.4%by generating an average output power of 2.5 dBm while only consuming 19.7 mW（including buffers）.The VCO exhibits a phase noise of-87 dBc/Hz at 1 MHz offset,leading to a figure of merit（FoM） of-167.5 dB/Hz and a tuning range of 3.8%（from 48.98 to 50.88 GHz）.
文摘This paper discusses the design of a fully differential 2.1 GHz CMOS low noise amplifier using the TSMC 0.25 μm CMOS process. Intended for use in 3G, the low noise amplifier is fully integrated and without off-chip components. The design uses an LC tank to replace a large inductor to achieve a smaller die area, and uses shielded pad capacitances to improve the noise performance. This paper also presents evaluation results of the design.
