A novel 2D analytical model for the doping profile of the bulk silicon RESURF LDMOS drift region is proposed. According to the proposed model, to obtain good performance, the doping profile in the total drift region o...A novel 2D analytical model for the doping profile of the bulk silicon RESURF LDMOS drift region is proposed. According to the proposed model, to obtain good performance, the doping profile in the total drift region of a RESURF LDMOS with a field plate should be piecewise linearly graded. The breakdown voltage of the proposed RESURF LDMOS with a piecewise linearly graded doping drift region is improved by 58. 8%, and the specific on-resistance is reduced by 87. 4% compared with conventional LDMOS. These results are verified by the two-dimensional process simulator Tsuprem-4 and the device simulator Medici.展开更多
A novel silicon-on-insulator（SOI） high breakdown voltage（BV） power device with interlaced dielectric trenches（IDT） and N/P pillars is proposed. In the studied structure, the drift region is folded by IDT embedde...A novel silicon-on-insulator（SOI） high breakdown voltage（BV） power device with interlaced dielectric trenches（IDT） and N/P pillars is proposed. In the studied structure, the drift region is folded by IDT embedded in the active layer,which results in an increase of length of ionization integral remarkably. The crowding phenomenon of electric field in the corner of IDT is relieved by the N/P pillars. Both traits improve two key factors of BV, the ionization integral length and electric field magnitude, and thus BV is significantly enhanced. The electric field in the dielectric layer is enhanced and a major portion of bias is borne by the oxide layer due to the accumulation of inverse charges（holes） at the corner of IDT.The average value of the lateral electric field of the proposed device reaches 60 V/μm with a 10 μm drift length, which increases by 200% in comparison to the conventional SOI LDMOS, resulting in a breakdown voltage of 607 V.展开更多
A new high-voltage LDMOS with folded drift region （FDR LDMOS） is proposed. The drift region is folded by introducing the interdigital oxide layer in the： Si active layer, the result of which is that the effective l...A new high-voltage LDMOS with folded drift region （FDR LDMOS） is proposed. The drift region is folded by introducing the interdigital oxide layer in the： Si active layer, the result of which is that the effective length of the drift region is increased significantly. The breakdown characteristic has been improved by the shielding effect of the electric field from the holes accumulated in the surface of the device and the buried oxide layer. The numerical results indicate that the breakdown voltage of 700 V is obtained in the proposed device in comparison to 300 V of conventional LDMOS, while maintaining low on-resistance.展开更多
对一种采用新结构的LDMOS(lateral double diffused metal oxide semiconductor)器件建立了模型.该器件在LDMOS中采用异质双栅(dual material gate,DMG)结构,这样使得该器件(DMG-LDMOS)同时具有LDMOS和DMG MOSFET的特性和优点.给出了DMG...对一种采用新结构的LDMOS(lateral double diffused metal oxide semiconductor)器件建立了模型.该器件在LDMOS中采用异质双栅(dual material gate,DMG)结构,这样使得该器件(DMG-LDMOS)同时具有LDMOS和DMG MOSFET的特性和优点.给出了DMG-LDMOS中沟道区表面电势和电场的一维表达式,并在此基础上考虑了大驱动电压下引入的沟道载流子速度过冲效应的影响,建立了基于物理的沟道电流模型.最后比较了Medici器件仿真结果和所建立的沟道电流模型,验证了该模型的可用性.展开更多
文摘A novel 2D analytical model for the doping profile of the bulk silicon RESURF LDMOS drift region is proposed. According to the proposed model, to obtain good performance, the doping profile in the total drift region of a RESURF LDMOS with a field plate should be piecewise linearly graded. The breakdown voltage of the proposed RESURF LDMOS with a piecewise linearly graded doping drift region is improved by 58. 8%, and the specific on-resistance is reduced by 87. 4% compared with conventional LDMOS. These results are verified by the two-dimensional process simulator Tsuprem-4 and the device simulator Medici.
基金Project supported by the Guangxi Natural Science Foundation of China(Grant Nos.2013GXNSFAA019335 and 2015GXNSFAA139300)Guangxi Experiment Center of Information Science of China(Grant No.YB1406)+2 种基金Guangxi Key Laboratory of Wireless Wideband Communication and Signal Processing of China,Key Laboratory of Cognitive Radio and Information Processing(Grant No.GXKL061505)Guangxi Key Laboratory of Automobile Components and Vehicle Technology of China(Grant No.2014KFMS04)the National Natural Science Foundation of China(Grant Nos.61361011,61274077,and 61464003)
文摘A novel silicon-on-insulator（SOI） high breakdown voltage（BV） power device with interlaced dielectric trenches（IDT） and N/P pillars is proposed. In the studied structure, the drift region is folded by IDT embedded in the active layer,which results in an increase of length of ionization integral remarkably. The crowding phenomenon of electric field in the corner of IDT is relieved by the N/P pillars. Both traits improve two key factors of BV, the ionization integral length and electric field magnitude, and thus BV is significantly enhanced. The electric field in the dielectric layer is enhanced and a major portion of bias is borne by the oxide layer due to the accumulation of inverse charges（holes） at the corner of IDT.The average value of the lateral electric field of the proposed device reaches 60 V/μm with a 10 μm drift length, which increases by 200% in comparison to the conventional SOI LDMOS, resulting in a breakdown voltage of 607 V.
基金Project supported by the State Key Laboratory of Electronic Thin Films and Integrated Devices,UESTC(No.KFJJ201205)the Guangxi Department of Education(No.201202ZD041)+1 种基金the China Postdoctoral Science Foundation(Nos.2012M521127,2013T60566)the National Natural Science Foundation of China(Nos.61361011,61274077,61464003)
文摘A new high-voltage LDMOS with folded drift region （FDR LDMOS） is proposed. The drift region is folded by introducing the interdigital oxide layer in the： Si active layer, the result of which is that the effective length of the drift region is increased significantly. The breakdown characteristic has been improved by the shielding effect of the electric field from the holes accumulated in the surface of the device and the buried oxide layer. The numerical results indicate that the breakdown voltage of 700 V is obtained in the proposed device in comparison to 300 V of conventional LDMOS, while maintaining low on-resistance.
文摘对一种采用新结构的LDMOS(lateral double diffused metal oxide semiconductor)器件建立了模型.该器件在LDMOS中采用异质双栅(dual material gate,DMG)结构,这样使得该器件(DMG-LDMOS)同时具有LDMOS和DMG MOSFET的特性和优点.给出了DMG-LDMOS中沟道区表面电势和电场的一维表达式,并在此基础上考虑了大驱动电压下引入的沟道载流子速度过冲效应的影响,建立了基于物理的沟道电流模型.最后比较了Medici器件仿真结果和所建立的沟道电流模型,验证了该模型的可用性.
