Novel LDNMOS embedded SCR with strong ESD robustness based on 0.5 μm 18 V CDMOS technology

A novel LDNMOS embedded silicon controlled rectifier(SCR) was proposed to enhance ESD robustness of high-voltage(HV) LDNMOS based on a 0.5 μm 18 V CDMOS process. A two-dimensional(2D) device simulation and a transmission line pulse(TLP) testing were used to analyze the working mechanism and ESD performance of the novel device. Compared with the traditional GG-LDNMOS, the secondary breakdown current(It2) of the proposed device can successfully increase from 1.146 A to 3.169 A with a total width of 50 μm, and ESD current discharge efficiency is improved from 0.459 m A/μm2 to 1.884 m A/μm2. Moreover, due to their different turn-on resistances(Ron), the device with smaller channel length(L) owns a stronger ESD robustness per unit area.

基于SOI工艺下600V LDNMOS的设计与分析

基于SOI工艺,运用SILVACO公司的工艺仿真(Athena)和器件仿真(Atlas)模拟软件,结合实际流片测试结果完成对600 V LDNMOS的设计和器件性能分析.整个器件采用环形版图结构,以优化器件的横向尺寸,漏端漂移区通过渐变掺杂技术(VLD)调节器件表面横向电场分布,并在漂移区上方加入一定厚度的槽氧层,从而增大器件的源漏击穿电压.流片测试结果(Vth=1.7 V,Idsat=48 mA,BV=550 V)表明,器件的各项指标基本达到预期目标,实现了设计和分析的目的.

一种基于超高压工艺的AC-DC芯片供电方案

基于TSMC的超高压工艺,提出了一种新颖的AC-DC芯片供电方案,省去了传统的辅助绕组,减小了PCB板承载系统的面积,拓宽了应用领域,节约了设计成本。芯片直接连接到高电压直流通路上,由芯片内部设计的控制逻辑来决定电流源对外接大电容的充放电,从而实现了一种动态的供电方案,大大简化了系统设计;通过电路优化设计,确保了简洁、无损耗的启动序列。