A comparative study of digital low dropout regulators

Granular power management in a power-efficient system on a chip(SoC)requires multiple integrated voltage regulators with a small area,process scalability,and low supply voltage.Conventional on-chip analog low-dropout regulators(ALDOs)can hardly meet these requirements,while digital LDOs(DLDOs)are good alternatives.However,the conventional DLDO,with synchronous control,has inherently slow transient response limited by the power-speed trade-off.Meanwhile,it has a poor power supply rejection(PSR),because the fully turned-on power switches in DLDO are vulnerable to power supply ripples.In this comparative study on DLDOs,first,we compare the pros and cons between ALDO and DLDO in general.Then,we summarize the recent DLDO advanced techniques for fast transient response and PSR enhancement.Finally,we discuss the design trends and possible directions of DLDO.

Dual Micro-power 150mA Ultra LDO CMOS Regulator with Fast Startup

This paper presents a dual micro-power 150mA ultra LDO CMOS regulator,which is designed for high performance and small size portable wireless devices.The proposed LDO has been designed and simulated in 0.5μm 2P3M CMOS Process.It can guarantee 150mA output current per circuit and the leakage voltage is 60mV,1nA quiescent current when both are in shutdown mode,and it has 115μA ground current,output noise is 42μVrms,130μs fast turn-on circuitry and the junction temperature range is-40℃to 125℃.

A dynamic-biased dual-loop-feedback CMOS LDO regulator with fast transient response

This paper presents a low-dropout regulator （LDO） for portable applications with dual-loop feedback and a dynamic bias circuit. The dual-loop feedback structure is adopted to reduce the output voltage spike and the response time of the LDO. The dynamic bias circuit enhances the slew rate at the gate of the power transistor. In addition, an adaptive miller compensation technique is employed, from which a single pole system is realized and over a 59~ phase margin is achieved under the full range of the load current. The proposed LDO has been implemented in a 0.6μm CMOS process. From the experimental results, the regulator can operate with a minimum dropout voltage of 200 mV at a maximum 300 mA load and IQ of 113μA. The line regulation and load regulation are improved to 0. l mV/V and 3.4 μV/mA due to the sufficient loop gain provided by the dual feedback loops. Under a full range load current step, the voltage spikes and the recovery time of the proposed LDO is reduced to 97 mV and 0.142 μs respectively.

A novel buck/LDO dual-mode DC–DC converter for efficiency improvement

A novel buck/LDO dual-mode （BLDM） converter using a multiplexing power MOS transistor is proposed, which adaptively switches between buck mode and LDO mode to improve conversion efficiency. The chip was fabricated in a standard 0.35 #m CMOS process. Measurement results show that the peak efficiency is 97%. For the light load operation, the efficiency is improved by 14%. The efficiency keeps higher than 82.5% for the load current of 50 mA without any complex control or extra EMI due to the normal method of pulse frequency modulation （PFM） control used for improving the light load efficiency. It does not cost much extra chip area because no additional regulator PMOS is needed. It is more suitable for noise-restricted systems and battery-powered electronic devices for when battery voltage drops because of long hours of work.

A transient-enhanced NMOS low dropout voltage regulator with parallel feedback compensation

This paper presents a transient-enhanced NMOS low-dropout regulator （LDO） for portable applications with parallel feedback compensation. The parallel feedback structure adds a dynamic zero to get an adequate phase margin with a load current variation from 0 to 1 A. A class-AB error amplifier and a fast charging/discharging unit are adopted to enhance the transient performance. The proposed LDO has been implemented in a 0.35 μm BCD process. From experimental results, the regulator can operate with a minimum dropout voltage of 150 mV at a maximum 1 A load and IQ of 165 μA. Under the full range load current step, the voltage undershoot and overshoot of the proposed LDO are reduced to 38 mV and 27 mV respectively.

A fully on-chip fast-transient NMOS low dropout voltage regulator with quasi floating gate pass element

This paper presents a fully on-chip NMOS low-dropout regulator（LDO） for portable applications with quasi floating gate pass element and fast transient response.The quasi floating gate structure makes the gate of the NMOS transistor only periodically charged or refreshed by the charge pump,which allows the charge pump to be a small economical circuit with small silicon area.In addition,a variable reference circuit is introduced enlarging the dynamic range of error amplifier during load transient.The proposed LDO has been implemented in a 0.35 μm BCD process.From experimental results,the regulator can operate with a minimum dropout voltage of 250 mV at a maximum 1 A load and Iq of 395 μA.Under full-range load current step,the voltage undershoot and overshoot of the proposed LDO are reduced to 50 and 26 mV,respectively.