An ISM 2.4 GHz low power low-IF RF receiver front-end

This paper describes the implementation ofan RF receiver front-end for the 2.4 GHz industrial scientific medical band under TSMC 0.13 μm CMOS technology; it comprises a low noise amplifier （LNA） which uses an added gate-source capacitor for low power performance and a dual-converter composed of a single-balanced active RF mixer and double-balanced passive IF mixer. Dual-down-conversion technique is used for reducing power. A 2.4 GHz low power low-IF RF receiver front-end is proposed. An LNA for rejecting image signal, an inductor- capacitor （LC） tank is used in series with source of input-stage transistor of the RF mixer, and combined with the LC load of the LNA, 30-dB image rejection is realized. Fabricated in a 0.13 μm CMOS process, the proposed chip occupies 0.42 mm2 area, achieves 4 dB noise figure, -22 dBm IIP3 and 37 dB voltage gain dissipating only 4.2-mW under 1.2-V supply.

Adaptive IF selection and IQ mismatch compensation in a low-IF GSM receiver

This paper presents an algorithm that can adaptively select the intermediate frequency（IF） and compensate the IQ mismatch according to the power ratio of the adjacent channel interference to the desired signal in a low-IF GSM receiver.The IF can be adaptively selected between 100 and 130 kHz.Test result shows an improvement of phase error from 6.78°to 3.23°.Also a least mean squares（LMS） based IQ mismatch compensation algorithm is applied to improve image rejection ratio（IRR） for the desired signal along with strong adjacent channel interference.The IRR is improved from 29.1 to 44.3 dB in measurement.The design is verified in a low-IF GSM receiver fabricated in SMIC 0.13μm RF CMOS process with a working voltage of 1.2 V.

A 2.4 GHz ultra-low power low-IF receiver and MUX-based transmitter for WPAN applications

This paper presents a 2.4 GHz CMOS transceiver for the wireless personal area network （WPAN） inte- grated in 0.18/zm CMOS technology. This transceiver adopts a low-IF receiver, a MUX based transmitter and a fast-setting fractional-N frequency synthesizer. For achieving low cost and low power consumption, an inductor- less receiver front-end, an adaptive analog baseband, a low power MUX and a current-reused phase-locked loop （PLL） have been proposed in this work. Measured results show that the receiver achieves-8 dBrn of lIP3 and 31 dB of image rejection. The transmitter delivers 0 dBm output power at a data rate of 2 Mbps. The current consumption is 7.2 mA in the receiving mode and 6.9 mA in the transmitting mode, respectively.

A CMOS G_m-C complex filter with a reconfigurable center and cutoff frequencies in low-IF WiMAX receivers

This paper presents a reconfigurable fifth-order complex Gm-C filter for different data rates in low-IF WiMAX applications.The design procedure and linearized measures to realize the complex filter are described.In order to achieve the reconfigurability of bandwidth window,the center frequency and the cutoff frequency filter are adjusted simultaneously by changing capacitor values while keeping transconductors unchanged.Also,the filter integrates an on-chip automatic frequency tuning circuit based on a PLL.Experimental results show that it has an IRR of 32 dB,a THD of -43 dB,and an input-referred noise of 21μVrms.The chip is fabricated in 0.13μm CMOS process,occupies 0.7×1 mm2,and consumes 4.8 mA current from a 1.2 V power supply.

一种多信道接收的信号处理新方法

提出一种多信道条件下带有LOW-IF接收机的新型模数信号处理方法,一般LOW-IF接收机中,镜频信号会对期望信号造成干扰。在本文方案下,由模拟复带通滤波器完成信道选择,干扰信号通过采用DLMS算法的FIR自适应滤波器消除。仿真分析表明,本文方案对AD转换器复杂度要求低,能很好抑制邻近信道信号干扰,提高系统性能。

A BFSK and OOK IF demodulation circuit with 2.8 μs settling time and re-configurable image rejection functions for MICS/BCC applications

A BFSK and OOK IF base-band circuit is provided to implement the low-IF RF receivers for a dualband MICS/BCC network controller. In order to transfer the massive vital data immediately, the IF circuit is comprised of the fast-settling feed-forward programmable gain amplifier（PGA）, a Gm-C complex filter, the fixed gain amplifier（FGA） and a 4-input ＂quadratic sum＂ demodulator. A novel auto-switched coarse gain-setting method is adopted in the PGA to enhance the reaction speed and narrow the output signal range. Also the PGA does not suffer the same stability constraint as open-loop topologies. The complex filter fulfills the function of image rejection,in which the center frequency and bandwidth can be adjusted individually. The FGA is used to ameliorate the linearity and the ＇quadratic sum＇ demodulator can reduce the overall power consumption. The designed IF circuit is fabricated with SMIC 0.18 μm CMOS process. The chip area is about 5.36 mm^2. Measurement results are given to verify the design goals.

A 0.18μm CMOS single-inductor single-stage quadrature frontend for GNSS receiver

This paper presents an improved merged architecture for a low-IF GNSS receiver frontend,where the bias current and functions are reused in a stacked quadrature LNA-mixer-VCO.Only a single spiral inductor is implemented for the LC resonator and an extra 1/2 frequency divider is added as the quadrature LO signal generator. The details of the design are presented.The gain plan and noise figure are discussed.The phase noise,quadrature accuracy and power consumption are improved.The test chip is fabricated though a 0.18μm RF CMOS process. The measured noise figure is 5.4 dB on average,with a gain of 43 dB and a IIP3 of-39 dBm.The measured phase noise is better than -105 dBc/Hz at 1 MHz offset.The total power consumption is 19.8 mW with a 1.8 V supply. The experimental results satisfy the requirements for GNSS applications.

A reconfigurable complex band-pass filter with improved passive compensation

This paper presents a 5th-order Chebyshev-I active RC complex filter for multi-mode multi-band global navigation satellite systems （GNSS） RF receivers. An improved passive compensation technique is used to cancel the excess phase lag of the integrators, thus ensuring the in-band flatness of the frequency response over various ambient conditions. The filter has a programmable gain from 0 to 42 dB with a 6 dB step, a tunable center fre- quency at either 6.4 MHz or 16 MHz, and a bandwidth from 2 to 20 MHz with less than 3% frequency uncertainty. Implemented in a 0.18μm CMOS process, the whole filter consumes 7.8 mA from a 1.8 V supply voltage and occupies a die area of 0.4 mm2.