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Mixed sensitivity H_∞ control for LTI systems with varying time delays
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作者 OULD MOHAMED Mohamed vall 《Journal of Systems Engineering and Electronics》 SCIE EI CSCD 2018年第3期611-617,共7页
Designing a robust controller for a system with timevarying delays poses a major challenge. In this paper, we propose a method based on mixed sensitivity H∞ for the control of linear time invariant(LTI) systems wit... Designing a robust controller for a system with timevarying delays poses a major challenge. In this paper, we propose a method based on mixed sensitivity H∞ for the control of linear time invariant(LTI) systems with varying time delays. The time delay is assumed bounded and the upper bound is known. In the technique we propose, the delay affecting the plant to be controlled is treated as an unmodeled uncertainty(in form of multiplicative uncertainty). That uncertainty is approximated and then an H∞based controller, for the plant represented by the multiplicative uncertainty and the nominal model, is calculated. The obtained H∞controller is used to control the LTI systems with varying time delays. Simulation examples are given to illustrate the effectiveness of the proposed method. 展开更多
关键词 linear time invariant(lti systems mixed sensitivity H∞ varying time delay unmodeled uncertainty H∞ control
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Design of high-speed and low-power finite-word-length PID controllers 被引量:1
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作者 A. K. OUDJIDA N. CHAILLET +2 位作者 A. LIACHA M. L. BERRANDJIA M. HAMERLAIN 《Control Theory and Technology》 EI CSCD 2014年第1期68-83,共16页
ASIC or FPGA implementation of a finite word-length PID controller requires a double expertise: in control system and hardware design. In this paper, we only focus on the hardware side of the problem. We show how to ... ASIC or FPGA implementation of a finite word-length PID controller requires a double expertise: in control system and hardware design. In this paper, we only focus on the hardware side of the problem. We show how to design configurable fixed-point PIDs to satisfy applications requiring minimal power consumption, or high control-rate, or both together. As multiply operation is the engine of PID, we experienced three algorithms: Booth, modified Booth, and a new recursive multi-bit multiplication algorithm. This later enables the construction of finely grained PID structures with bit-level and unit-time precision. Such a feature permits to tailor the PID to the desired performance and power budget. All PIDs are implemented at register-transfer4evel (RTL) level as technology-independent reusable IP-cores. They are reconfigurable according to two compilemtime constants: set-point word-length and latency. To make PID design easily reproducible, all necessary implementation details are provided and discussed. 展开更多
关键词 Design-reuse Embedded finite-word-length (FWL) controllers Intellectual property (IP) Linear time invariant lti systems Low-power and speed optimization PID
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