A Photolithography Process Design for 5 nm Logic Process Flow

With the introduction of EUV lithography,the photolithographic process in 5 nm logic process can be simplified to use mostly single exposure method.In a typical 5 nm logic process,the contact-poly pitch(CPP)is 44-50 nm,the minimum metal pitch(MPP)is around 30-32 nm.And the overlay budget is estimated to be 2.5 nm(on product overlay).Although the optical resolution of a 0.33NA exposure tool(such as ASML NXE3400)can reach below 32 nm pitch,stochastics in the EUV absorption in photoresists has limited its application to smaller pitches.For the CPP mentioned above,one can use 193 nm immersion lithography with Self-Aligned Double Patterning(SADP)technique to provide good image contrast(or CDU,LWR)as well as good overlay,as for the 10 and 7 nm generations.In the BEOL,however,the 30-32 pitch cannot be realized by a single EUV exposure with enough printing defect process window.If this pitch is to be done by 193 nm immersion lithography,more than 6-8 exposures are needed with very complicated overlay result.For EUV,this can be done through self-aligned LELE with both good CD and overlay control.We have done an optimization of the photolithographic process parameters for the typical metal with a self-developed aerial image simulator based on rigorous coupled wave analysis(RCWA)algorithm and the Abbe imaging routine with an EUV absorption model which describes stochastics.We have calibrated our model with wafer exposure data from several photoresists under collaboration with IMEC.As we have presented last year,to accommodate all pitches under a logic design rule,as well as to provide enough CDU for the logic device performance,in DUV lithography,a typical minimum exposure latitude(EL)for the poly and metal layers can be set at,respectively,18%and 13%.In EUV,due to the existence of stochastics,13%EL,which corresponds to an imaging contrast of 40%,seems not enough for the metal trenches,and to obtain an imaging contrast close to 100%,which yields an EL of 31.4%means that we need to relax minimum pitch to above 41 nm(conventional imaging limit for 0.33NA).This is the best imaging contrast a photolithographic process can provide to reduce LWR and stochastics.In EUV,due to the significantly smaller numerical apertures compared to DUV,the aberration impact can cause much more pronounced image registration error,in order to satisfy 2.5 nm total overlay,the aberration induced shift needs to be kept under 0.2 nm.We have also studied shadowing effect and mask 3D scattering effect and our results will be provided for discussion.

Key Process Approach Recommendation for 5 nm Logic Process Flow with EUV Photolithography

5 nm logic process is the current leading-edge technology which is under development in world-wide leading foundries.In a typical 5 nm logic process,the Fin pitch is 22~27 nm,the contact-poly pitch(CPP)is 48?55 nm,and the minimum metal pitch(MPP)is around 30~36 nm.Due to the fact that these pitches are much smaller than the resolution capability of 193 nm immersion lithography,it is also the first generation which adopts EUV photolithography technology on a large-scale where the process flow can be simplified by single exposure method from more than 10 layers.Relentless scaling brings big challenges to process integration and pushes each process module to the physical and material limit.Therefore,the success of process development will largely depend on careful balance the pros and cons to achieve both performance and yield targets.In the paper,we discussed the advantages and disadvantages of different process approaches for key process loops for 5 nm logic process flow,including dummy poly cut versus metal gate cut approaches in the metal gate loops,self-aligned contact(SAC)versus brutally aligned contact(BAC)approaches,and also introduced the self-aligned double patterning approach in the lower metal processes.Based on the above evaluation,we will provide a recommendation for module's process development.