Compressive Measurement Identification of Linear Time-Invariant System Application in DC Motor

In traditional system identification (SI), actual values of system parameters are concealed in the input and output data;hence, it is necessary to apply estimation methods to determine the parameters. In signal processing, a signal with N elements must be sampled at least N times. Thus, most SI methods use N or more sample data to identify a model with N parameters;however, this can be improved by a new sampling theory called compressive sensing (CS). Based on CS, an SI method called compressive measurement identification (CMI) is proposed for reducing the data needed for estimation, by measuring the parameters using a series of linear measurements, rather than the measurements in sequence. In addition, the accuracy of the measurement process is guaranteed by a criterion called the restrict isometric principle. Simulations demonstrate the accuracy and robustness of CMI in an underdetermined case. Further, the dynamic process of a DC motor is identified experimentally, establishing that CMI can shorten the identification process and increase the prediction accuracy.

Controllability, Observability and Stability for a Class of Fractional-Order Linear Time-Invariant Control Systems

The definitions of controllability, observability and stability were presented for fractional-order linear systems. Using the Cayley-Hamilton theorem and Mittag-Leffler function in two parameters, the sufficient and necessary conditions of controllability and observability for such systems were derived. In terms of Lyapunov’s stability theory, using the theorems of Mittage-Leffler function in two parameters this paper directly derived the sufficient and necessary condition of stability for such systems. The results obtained are useful for the analysis and synthesis of fractional-order linear control systems.

The identification algorithm for commensurate order linear time-invariant fractional systems

An efficient identification algorithm is given for commensurate order linear time-invariant fractional systems. This algorithm can identify not only model coefficients of the system, but also its differential order at the same time. The basic idea is to change the system matrix into a diagonal one through basis transformation. This makes it possible to turn the system’s input-output relationships into the summation of several simple subsystems, and after the identification of these subsystems, the whole identification system is obtained which is algebraically equivalent to the former system. Finally an identification example verifies the effectiveness of the method previously mentioned.

Perturbation Analysis of Continuous-Time Linear Time-Invariant Systems

In this paper, we consider the perturbation analysis of linear time-invariant systems, which arise from the linear optimal control in continuous-time. We provide a method to compute condition numbers of continuous-time linear time-invariant systems. It solves the perturbed linear time-invariant systems via Riccati differential equations and continuous-time algebraic Riccati equations in finite and infinite time horizons. We derive the explicit expressions of measuring the perturbation bounds of condition numbers with respect to the solution of the linear time-invariant systems. Furthermore, condition numbers and their upper bounds of Riccati differential equations and continuous-time algebraic Riccati equations are also discussed. Numerical simulations show the sharpness of the perturbation bounds computed via the proposed methods.

Efficient Interconnect Network Model for Linear Circuit Reduction

A new interconnect network model for linear netw ork reduction is presented.In this new model,the ports of the interconnect network are classified into two groups:active and passive ports.After the classification,some proprieties of the interconnect network are found to be redundant and pruned before reduction.For common interconnect networks,the scale of reduced models is smaller than 50% of the scale of previous works.

A novel mixed-synchronization phenomenon in coupled Chua's circuits via non-fragile linear control

Dynamical variables of coupled nonlinear oscillators can exhibit different synchronization patterns depending on the designed coupling scheme. In this paper, a non-fragile linear feedback control strategy with multiplicative controller gain uncertainties is proposed for realizing the mixed-synchronization of Chua＇s circuits connected in a drive-response configuration. In particular, in the mixed-synchronization regime, different state variables of the response system can evolve into complete synchronization, anti-synchronization and even amplitude death simultaneously with the drive variables for an appropriate choice of scaling matrix. Using Lyapunov stability theory, we derive some sufficient criteria for achieving global mixed-synchronization. It is shown that the desired non-fragile state feedback controller can be constructed by solving a set of linear matrix inequalities （LMIs）. Numerical simulations are also provided to demonstrate the effectiveness of the proposed control approach.

Electromagnetic Analysis and Optimization of High-speed Maglev Linear Synchronous Motor Based on Field-circuit Coupling

High speed maglev train has become a new non-contact transportation mode mainly studied in recent years because of its non-sticking and high speed characteristics.Firstly,the finite element model of the long stator linear synchronous motor(LSM)is established based on the structure of the test prototype.After calculation,it is compared with the experimental data and verified.On this basis,a field-circuit coupling model based on inverter circuit is established,and the influence of carrier wave ratio change on the output characteristics of LSM is calculated and analyzed.Finally,the filter circuit is introduced into the field-circuit coupling model,and the influence of the filter circuit on the output characteristics of the LSM is compared and analyzed.

Influence of Tilted Angle on Effective Linear Energy Transfer in Single Event Effect Tests for Integrated Circuits at 130 nm Technology Node

A heavy-ion irradiation experiment is studied in digital storage cells with different design approaches in 130？nm CMOS bulk Si and silicon-on-insulator （SOI） technologies. The effectiveness of linear energy transfer （LET） with a tilted ion beam at the 130？nm technology node is obtained. Tests of tilted angles θ=0 ° , 30 ° and 60 ° with respect to the normal direction are performed under heavy-ion Kr with certain power whose LET is about 40？MeVcm 2 /mg at normal incidence. Error numbers in D flip-flop chains are used to determine their upset sensitivity at different incidence angles. It is indicated that the effective LETs for SOI and bulk Si are not exactly in inverse proportion to cosθ , furthermore the effective LET for SOI is more closely in inverse proportion to cosθ compared to bulk Si, which are also the well known behavior. It is interesting that, if we design the sample in the dual interlocked storage cell approach, the effective LET in bulk Si will look like inversely proportional to cosθ very well, which is also specifically explained.

THE NEW SUPER-HIGH-SPEED DIGITAL CIRCUIT BASED ON LINEAR AND-OR GATES

The paper reveals the relation between the linear AND-OR gate and the emitter function logic. With theoretic calculation and PSPICE simulation, the paper proves that the linear AND-OR gates can work at super-high-speed and can be multi-cascaded. On the basis of analyzing the high-speed switch units which coordinate with linear AND-OR gates, two kinds of emitter coupled logic circuits are designed. The paper also discusses the design principles of super-high-speed digital circuits, and some examples of combinational and sequential circuits using linear AND-OR gate are given.

Radio Frequency Low Noise Amplifier with Linearizing Bias Circuit

A 1.34 GHz-1=60 MHz low noise amplifier （LNA） designed in a 0.35 pm SiGe process is presented. The designed LNA exhibits a power gain of 21.46 dB and a noise figure （NF） of 1.27 dB at 1.34 GHz. The linearity is improved with an active biasing technique. The post-layout simulation shows an input referred 1-dB compression point （IPldn） of-11.52 dBm. Compared with the recent reported high gain LNAs, the proposed LNA has a much better linearity without degrading other performance. The LNA draws 10 mA current from a 3.3 V power supply.

Nonlinear Resistance Circuit Subsection Linearity Decomposition Fitting Analysis

The analysis of circuits is frequently required in the electricity of physics. When analyzing circuits, the general idea is to study the issues related to nonlinear resistance circuits based on commonly used physical and electrical theory. Generally, circuits can be divided into linear resistance circuits and nonlinear resistance circuits. However, for some nonlinear resistance circuit, a small part of them are decomposed through subsection linearity while most of them are adopted the form of hieroglyph combination for subsection decomposition fitting analysis. For the following contents, the author will adopt curve layout method to analyze nonlinear resistance element and relation characteristics of voltage and current;to state the characteristics and nature of common electronic elements in our life, and concepts of concave resistance and convex resistance;to analyze the characteristics of nonlinear resistance circuits through electrical circuit analysis method based on the electrical theorem of physics;finally, to analyze referring to actual cases, study the veracity, verify the feasibility and scientificity of the adopted analytical approach, apply image graphics of the resistance circuits in the convenient way to solve complicated design problems among actual electrical problems.

CANONICAL PIECEWISE-LINEAR ANALYSIS FOR NONLINEAR DC FAULT CIRCUITS

This paper uses canonical piecewise-linear analysis method to analyze nonlinear DC fault circuitsand solve for the values of the test port voltages which are selected beforehand .The method needs lessmemory storages,obtains the results in finite steps and has high efficiency in computation.It can be appliedto the circuits containing multiport nonlinear elements.It is a good method of pre-test analysis for fault cir-cuits in simulation-before-test aproach in analogue circuit diagnosis.

Quantum fluctuations of mesoscopic damped double resonance RLC circuit with mutual capacitance-inductance coupling

Based on the scheme of damped harmonic oscillator quantization and thermo-field dynamics （TFD）, the quantization of mesoscopic damped double resonance RLC circuit with mutual capacitance-inductance coupling is proposed. The quantum fluctuations of charge and current of each loop in a squeezed vacuum state are studied in the thermal excitation case. It is shown that the fluctuations not only depend on circuit inherent parameters, but also rely on excitation quantum number and squeezing parameter. Moreover, due to the finite environmental temperature and damped resistance, the fluctuations increase with the temperature rising, and decay with time.

Numerical Analysis of the Output-Pulse Shaping Capability of Linear Transformer Drivers

Output-pulse shaping capability of a linear transformer driver （LTD） module under different conditions is studied, by conducting the whole circuit model simulation by using the PSPICE code. Results indicate that a higher impedance profile of the internal transmission line would lead to a wider adjustment range for the output current rise time and a narrower adjustment range for the current peak. The number of cavities in series has a positive effect on the output- pulse shaping capability of LTD. Such an improvement in the output-pulse shaping capability can primarily be ascribed to the increment in the axial electric length of LTD. For a triggering time interval longer than the time taken by a pulse to propagate through the length of one cavity, the output parameters of LTD could be improved significantly. The present insulating capability of gas switches and other elements in the LTD cavities may only tolerate a slightly longer deviation in the triggering time interval. It is feasible for the LTD module to reduce the output current rise time, though it is not useful to improve the peak power effectively.

Influences of Switching Jitter on the Operational Performances of Linear Transformer Drivers-Based Drivers

A whole circuit model of a linear transformer drivers （LTD） module composed of 60 cavities in series was developed in the software PSPICE to study the influence of switching jitter on the operational performances of LTDs. In the model, each brick in each cavity is capable of operating with jitter in its switch. Additionally, the manner of triggering cables entering into cavities was considered. The performances of the LTD module operating with three typical cavity-triggering sequences were simulated and the simulation results indicate that switching jitter affects slightly the peak and starting time of the output current pulse. However, the enhancement in switching jitter would significantly lengthen the rise time of the output current pulse. Without considering other factors, a jitter lower than 10 ns may be necessary for the switches in the LTD module to provide output current parameters with an acceptable deviation.

DECISION OF OPTIMAL HOPFIELD NEURAL NETWORK MODEL OF COMBINATIONAL CIRCUITS

By use of Hopfield model and basis solution of homogeneous linear equations which are established in accordance with consistent state, a practical decision method for the existence of optimal Hopfield model of combinational circuits is provided. Finally, an example is given.

Transformer Characteristics of Linear Motor-Transformer Apparatus

The characteristics of linear transformer are studied analytically. The transformer is composed in one of modes of linear motor-transformer apparatus proposed for future wireless light rail vehicle (LRV). The secondary (onboard) power factor can be adjusted at any value by an onboard converter. The equivalent circuit is used to study the transferred power control. The parameters are determined by three-dimensional finite element method (FEM) analysis for one pole-pair model. Under the rated primary (input) and secondary voltage and current, which are specified for linear motor operation, the characteristics of the secondary power factor are cleared. It is also shown that the input capacitor can improve the primary power factor and decrease the input power capacity, but does not change the efficiency. This linear transformer has the efficiency of 91% and the input power factor of 0.87 when the apparatus without input capacitor is controlled at the secondary power factor of 0.4.

THE DESIGN OF HIGH PERFORMANCE LINEAR TRANSCONDUCTOR

An improved structure of linear transconductor is presented in this paper. It is analyzed in theory and simulated with Spectre based on 0.25μm CMOS process. The simulation results show that the differential input voltage of the proposed transconductor is 4.0Vpp(peak to peak), whereas the differential input voltage of the existing source degeneration structure is 2.2Vpp, when their nonlinear errors are required to be less than 0.15%.

Optimizing the Stage Resolution of a 10-Bit, 50 Ms/Sec Pipelined A/D Converter &Its Impact on Speed, Power, Area, and Linearity

At high speeds and high resolution, the Pipeline ADCs are becoming popular. The options of different stage resolutions in Pipelined ADCs and their effect on speed, power dissipation, linearity and area are discussed in this paper. The basic building blocks viz. Op-Amp Sample and Hold circuit, sub converter, D/A Converter and residue amplifier used in every stage is assumed to be identical. The sub converters are implemented using flash architectures. The paper implements a 10-bit 50 Mega Samples/Sec Pipelined A/D Converter using 1, 1.5, 2, 3, 4 and 5 bits/stage conversion techniques and discusses about its impact on speed, power, area, and linearity. The design implementation uses 0.18 μm CMOS technology and a 3.3 V power supply. The paper concludes stating that a resolution of 2 bits/stage is optimum for a Pipelined ADC and to reduce the design complexity, we may go up to 3 bits/stage.