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Development of a Novel Noise Reduction Algorithm for Smart Checkout RFID System in Retail Stores
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作者 Shazielya Shamsul Mohammed A.H.Ali +2 位作者 Salwa Hanim Abdul-Rashid Atef M.Ghaleb Fahad M.Alqahtani 《Computers, Materials & Continua》 SCIE EI 2024年第7期1277-1304,共28页
This paper presents a smart checkout system designed to mitigate the issues of noise and errors present in the existing barcode and RFID-based systems used at retail stores’checkout counters.This is achieved by integ... This paper presents a smart checkout system designed to mitigate the issues of noise and errors present in the existing barcode and RFID-based systems used at retail stores’checkout counters.This is achieved by integrating a novel AI algorithm,called Improved Laser Simulator Logic(ILSL)into the RFID system.The enhanced RFID system was able to improve the accuracy of item identification,reduce noise interference,and streamline the overall checkout process.The potential of the systemfor noise detection and elimination was initially investigated through a simulation study usingMATLAB and ILSL algorithm.Subsequently,it was deployed in a small-scale environment to validate its real-world performance.Results show that RFID with the proposed new algorithm ILSL and AI basket is capable of accurately detecting the related itemswhile eliminating noise originating fromunrelated objects,achieving an accuracy rate of 88%. 展开更多
关键词 Smart checkout system RFID technology improved laser simulator logic(ILSL) reduce noise checkout process
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GA-BASED MAXIMUM POWER DISSIPATION ESTIMATION OF VLSI SEQUENTIAL CIRCUITS OF ARBITRARY DELAY MODELS
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作者 Lu Junming Lin Zhcnghui (LSI Research Institute, Shanghai Jiaotong University, Shanghai 200030) 《Journal of Electronics(China)》 2002年第4期378-386,共9页
In this paper, the glitching activity and process variations in the maximum power dissipation estimation of CMOS circuits are introduced. Given a circuit and the gate library, a new Genetic Algorithm (GA)-based techni... In this paper, the glitching activity and process variations in the maximum power dissipation estimation of CMOS circuits are introduced. Given a circuit and the gate library, a new Genetic Algorithm (GA)-based technique is developed to determine the maximum power dissipation from a statistical point of view. The simulation on 1SCAS-89 benchmarks shows that the ratio of the maximum power dissipation with glitching activity over the maximum power under zero-delay model ranges from 1.18 to 4.02. Compared with the traditional Monte Carlo-based technique, the new approach presented in this paper is more effective. 展开更多
关键词 CMOS sequential circuits Maximum power dissipation estimation Genetic algorithm logic simulation Monte-Carlo technique
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