Programmable Logic Array (PLA) is an important building circuit of VLSI chips and some of the FPGA architectures have evolved from the basic PLA architectures. In this letter, a dynamic and static mixed PLA with singl...Programmable Logic Array (PLA) is an important building circuit of VLSI chips and some of the FPGA architectures have evolved from the basic PLA architectures. In this letter, a dynamic and static mixed PLA with single-phased clock is presented. Combining both dynamic and static design style rather than introducing additional interface-buffers overcomes the racing problem, thereby saves the chip area. Besides inheriting the advantages of dynamic circuit-low power dissipation and compact structure, this approach also provides high-speed operation.展开更多
The charge storage characteristics of P-channel Ge/Si hetero-nanocrystal based MOSFET memory has been investigated and a logical array has been constructed using this memory cell. In the case of the thickness of tunne...The charge storage characteristics of P-channel Ge/Si hetero-nanocrystal based MOSFET memory has been investigated and a logical array has been constructed using this memory cell. In the case of the thickness of tunneling oxide Tox = 2 nm and the dimensions of Si- and Ge-nanocrystal Dsi = DGe = 5 nm, the retention time of this device can reach ten years(～1 × 108 s) while the programming and erasing time achieve the orders of microsecond and millisecond at the control gate voltage | Vg | = 3 V with respect to N-wells,respectively. Therefore, this novel device, as an excellent nonvolatile memory operating at room temperature,is desired to obtain application in future VLSI.展开更多
In this paper, an improvement has been made on the algorithm of solving the kernels of new functions which are generated after a common divisor appearing in the original functions is replaced by a new intermediate var...In this paper, an improvement has been made on the algorithm of solving the kernels of new functions which are generated after a common divisor appearing in the original functions is replaced by a new intermediate variable. And an efficient method based on kernel heritage is presented. This method has been successfully used in synthesis of LCA (Logic Cell Array).展开更多
基金Supported by the Commission of Science Technology and Industry for National Defense and the National Natural Science Foundation of China (No. 90307011)
文摘Programmable Logic Array (PLA) is an important building circuit of VLSI chips and some of the FPGA architectures have evolved from the basic PLA architectures. In this letter, a dynamic and static mixed PLA with single-phased clock is presented. Combining both dynamic and static design style rather than introducing additional interface-buffers overcomes the racing problem, thereby saves the chip area. Besides inheriting the advantages of dynamic circuit-low power dissipation and compact structure, this approach also provides high-speed operation.
文摘The charge storage characteristics of P-channel Ge/Si hetero-nanocrystal based MOSFET memory has been investigated and a logical array has been constructed using this memory cell. In the case of the thickness of tunneling oxide Tox = 2 nm and the dimensions of Si- and Ge-nanocrystal Dsi = DGe = 5 nm, the retention time of this device can reach ten years(～1 × 108 s) while the programming and erasing time achieve the orders of microsecond and millisecond at the control gate voltage | Vg | = 3 V with respect to N-wells,respectively. Therefore, this novel device, as an excellent nonvolatile memory operating at room temperature,is desired to obtain application in future VLSI.
文摘In this paper, an improvement has been made on the algorithm of solving the kernels of new functions which are generated after a common divisor appearing in the original functions is replaced by a new intermediate variable. And an efficient method based on kernel heritage is presented. This method has been successfully used in synthesis of LCA (Logic Cell Array).
