A review on the design of ternary logic circuits

A multi-valued logic system is a promising alternative to traditional binary logic because it can reduce the complexity,power consumption, and area of circuit implementation. This article briefly summarizes the development of ternary logic and its advantages in digital logic circuits. The schemes, characteristics, and application of ternary logic circuits based on CMOS, CNTFET, memristor, and other devices and processes are reviewed in this paper, providing some reference for the further research and development of ternary logic circuits.

DESIGN OF TWO-PHASE SINUSOIDAL POWER CLOCK AND CLOCKED TRANSMISSION GATE ADIABATIC LOGIC CIRCUIT

First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked Transmission Gate Adiabatic Logic （CTGAL） circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor （NMOS） and Complementary Metal Oxide Semiconductor （CMOS） latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company （TSMC） 0.25um CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic （BCRL） and Pass-transistor Adiabatic Logic （PAL） including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.

A novel circuit design for complementary resistive switch-based stateful logic operations

Recently, it has been demonstrated that memristors can be utilized as logic operations and memory elements. In this paper, we present a novel circuit design for complementary resistive switch（CRS）-based stateful logic operations. The proposed circuit can automatically write the destructive CRS cells back to the original states. In addition, the circuit can be used in massive passive crossbar arrays which can reduce sneak path current greatly. Moreover, the steps for CRS logic operations using our proposed circuit are reduced compared with previous circuit designs. We validate the effectiveness of our scheme through Hspice simulations on the logic circuits.

A weighted averaging method for signal probability of logic circuit combined with reconvergent fan-out structures

By analyzing the structures of circuits,a novel approach for signal probability estimation of very large-scale integration(VLSI)based on the improved weighted averaging algorithm(IWAA)is proposed.Considering the failure probability of the gate,first,the first reconvergent fan-ins corresponding to the reconvergent fan-outs were identified to locate the important signal correlation nodes based on the principle of homologous signal convergence.Secondly,the reconvergent fan-in nodes of the multiple reconverging structure in the circuit were identified by the sensitization path to determine the interference sources to the signal probability calculation.Then,the weighted signal probability was calculated by combining the weighted average approach to correct the signal probability.Finally,the reconvergent fan-out was quantified by the mixed-calculation strategy of signal probability to reduce the impact of multiple reconvergent fan-outs on the accuracy.Simulation results on ISCAS85 benchmarks circuits show that the proposed method has approximate linear time-space consumption with the increase in the number of the gate,and its accuracy is 4.2%higher than that of the IWAA.

A highly sensitive ratiometric near-infrared nanosensor based on erbium-hyperdoped silicon quantum dots for iron(Ⅲ) detection

Ratiometric fluorescent detection of iron(Ⅲ)(Fe^(3+))offers inherent self-calibration and contactless analytic capabilities.However,realizing a dual-emission near-infrared(NIR)nanosensor with a low limit of detection(LOD)is rather challenging.In this work,we report the synthesis of water-dispersible erbium-hyperdoped silicon quantum dots(Si QDs:Er),which emit NIR light at the wavelengths of 810 and 1540 nm.A dual-emission NIR nanosensor based on water-dispersible Si QDs:Er enables ratiometric Fe^(3+)detection with a very low LOD(0.06μM).The effects of pH,recyclability,and the interplay between static and dynamic quenching mechanisms for Fe^(3+)detection have been systematically studied.In addition,we demonstrate that the nanosensor may be used to construct a sequential logic circuit with memory functions.

Two-Dimensional Tellurium:Progress,Challenges,and Prospects

Since the successful fabrication of two-dimensional(2D)tellurium(Te)in 2017,its fascinating properties including a thickness dependence bandgap,environmental stability,piezoelectric effect,high carrier mobility,and photoresponse among others show great potential for various applications.These include photodetectors,field-effect transistors,piezoelectric devices,modulators,and energy harvesting devices.However,as a new member of the 2D material family,much less known is about 2D Te compared to other 2D materials.Motivated by this lack of knowledge,we review the recent progress of research into 2D Te nanoflakes.Firstly,we introduce the background and motivation of this review.Then,the crystal structures and synthesis methods are presented,followed by an introduction to their physical properties and applications.Finally,the challenges and further development directions are summarized.We believe that milestone investigations of 2D Te nanoflakes will emerge soon,which will bring about great industrial revelations in 2D materials-based nanodevice commercialization.

Increase the Quality of Life through the Development of Automation

This paper discusses needs for the automation of the underdevelopment communities.The novelty of this research is the link between production of microprocessors and increasing of the life quality.This study highlights the importance of efficient and economic architecture of logical circuits for the automation.The aim of this research is to produce a logical circuit,which includes suitable gates.The circuit will be embedded in the automatic devices as a microprocessor to cause programmed functions.This research reports analytically a workshop method to build the circuit.It uses an assembly card and required gates.Then,it suggests certain VHDL codes to drive a motor.The workshop presents the configuration schemes and connection board for every gate.In addition,it shows a schematic wiring diagram of the circuit.Finally,the economic analysis proves the mass production of the circuit will enhance the automation and consequently the quality of life.The outcome of this research is a helpful experience to the engineers,manufacturers and students of the relevant disciplines to resolve the inequality in the use of the modern technologies.

Design and Implementation of Efficient Reversible Arithmetic and Logic Unit

In computing architecture, ALU plays a major role. Many promising applications are possible with ATMEGA microcontroller. ALU is a part of these microcontrollers. The performance of these microcontrollers can be improved by applying Reversible Logic and Vedic Mathematics. In this paper, an efficient reversible Arithmetic and Logic Unit with reversible Vedic Multiplier is proposed and the simulation results show its effectiveness in reducing quantum cost, number of gates, and the total number of logical calculations.

Design and Implementation of an Efficient Reversible Comparator Using TR Gate

Reversible logic is a new emerging technology with many promising applications in optical information processing, low power (Complementary Metal Oxide Semiconductor) CMOS design, (De Oxy RiboNucleic Acid) DNA computing, etc. In industrial automation, comparators play an important role in segregating faulty patterns from good ones. In previous works, these comparators have been implemented with more number of reversible gates and computational complexity. All these comparators use propagation technique to compare the data. This will reduce the efficiency of the comparators. To overcome the problem, this paper proposes an efficient comparator using (Thapliyal Ranganathan) TR gate utilizing full subtraction and half subtraction algorithm which will improve the computation efficiency. The comparator design using half subtraction algorithm shows an improvement in terms of quantum cost. The comparator design using full subtraction algorithm shows effectiveness in reducing number of reversible gates required and garbage output.

Atomic layer deposited 2D MoS2 atomic crystals:From material to circuit

Atomic layer deposition(ALD)can be used for wafer-scale synthesis of 2D materials.In this paper,a novel,reliable,secure,low-cost,and high-efficiency process for the fabrication of MoS2 is introduced and investigated.The resulting 2D materials show high carrier-mobility as well as excellent electrical uniformity.Using molybdenum pentachloride(MoCl5)and hexamethyldisilathiane(HMDST)as ALD precursors,thickness-controlled MoS2 films are uniformly deposited on a 50 mm sapphire and a 100 mm silica substrate.This is done with a high growth-rate(up to 0.90Å/cycle).Large-scale top-gated FET arrays are fabricated using the films,with a room-temperature mobility of 0.56 cm2/(V·s)and a high on/off current ratio of 106.Excellent electrical uniformity is observed in the whole sapphire wafer.Additionally,logical circuits,including inverters,NAND,AND,NOR,and OR gates,are realized successfully with a high-k HfO2 dielectric layer.Our inverters exhibit a fast response frequency of 50 Hz and a DC-voltage gain of 4 at VDD=4 V.These results indicate that the new method has the potential to synthesize high quality MoS2 films on a large-scale,with hypo-toxicity and enhanced efficiency,which can facilitate a broader range of applications in the future.

Tribotronic triggers and sequential logic circuits

In this paper, a floating-gate tribotronic transistor （FGTT） based on a mobile triboelectric layer and a traditional silicon-based field-effect transistor （FET） is proposed. In the FGTT, the triboelectric charges in the layer created by contact electrification can be used to modulate charge carrier transport in the transistor. Based on the FGTTs and FETs, a tribotronic negated AND （NAND） gate that achieves mechanical-electrical coupled inputs, logic operations, and electrical level outputs is fabricated. By further integrating tribotronic NAND gates with traditional digital circuits, several basic units such as the tribotronic S-R trigger, D trigger, and T trigger have been demonstrated. Additionally, tribotronic sequential logic circuits such as registers and counters have also been integrated to enable external contact triggered storage and computation. In contrast to the conventional sequential logic units controlled by electrical signals, contact-triggered tribotronic sequential logic circuits are able to realize direct interaction and integration with the external environment. This development can lead to their potential application in micro/nano-sensors, electromechanical storage, interactive control, and intelligent instrumentation.

On the operating speed and energy efficiency of GaN-based monolithic complementary logic circuits for integrated power conversion systems

Gallium nitride(GaN)-based power conversion systems exhibit striking competitiveness in realizing compact and high-efficiency power management modules.Recently emerging GaN-based p-channel field-effect transistors(FETs)and monolithic integration techniques enable the implementation of GaN-based complementary logic(CL)circuits and thereby offer an additional pathway to improving the system-level energy efficiency and functional-ity.In this article,holistic analyses are conducted to evaluate the potential benefits of introducing GaN CL circuits into the integrated power systems,based on the material limit of GaN and state-of-the-art experimental results.It is revealed that the propagation delay of a single-stage CL gate based on the commercial p-GaN gate power HEMT(high-electron-mobility transistor)platform could be as short as sub-nanosecond,which sufficiently satis-fies the requirement of power conversion systems typically with operating frequencies less than 10 MHz.With the currently adopted n-FET-based logic gates(e.g.,directly coupled FET logic)replaced by CL gates,the power consumption of peripheral logic circuits could be substantially suppressed by more than 10^(3) times,mainly due to the elimination of the pronounced static power loss.Consequently,the energy efficiency of the entire system could be substantially improved.

Zero-static-power nonvolatile logic-in-memory circuits for flexible electronics

Flexible logic circuits and memory with ultra-low static power consumption are in great demand for battery-powered flexible electronic systems. Here, we show that a flexible nonvolatile logic-in-memory circuit enabling normally-off computing can be implemented using a poly（1,3,5-trivinyl-l,3,5-trimethyl cyclotrisiloxane） （pV3D3）-based memristor array. Although memristive logic-in-memory circuits have been previously reported, the requirements of additional components and the large variation of memristors have limited demonstrations to simple gates within a few operation cycles on rigid substrates only. Using memristor-aided logic （MAGIC） architecture requiring only memristors and pV3D3-memristor with good uniformity on a flexible substrate, for the first time, we experimentally demonstrated our implementation of MAGIC-NOT and -NOR gates during multiple cycles and even under bent conditions. Other functions, such as OR, AND, NAND, and a half adder, are also realized by combinations of NOT and NOR gates within a crossbar array. This research advances the development of novel computing architecture with zero static power consumption for battery- powered flexible electronic systems.

An approach to predicting dynamic power dissipation of coupled interconnect network in dynamic CMOS logic circuits

In deep submicron (DSM) integrated circuits (IC), coupling capacitors between interconnects become dominant over grounded capacitors. As a result, the dynamic power dissipation of one node is no longer only in relation to the signal on that node, and it also depends on signals on its neighbor nodes through coupling capacitors. Thus, for their limitation in dealing with ca-pacitively coupled nets, past jobs on power estimation are facing rigorous challenges and need to be ameliorated. This paper proposes and proves a simple and fast approach to predicting dynamic power dissipation of coupled interconnect networks: a coupling capacitor in dynamic CMOS logic circuits is decoupled and mapped into an equivalent cell containing an XOR gate and a grounded capacitor, and the whole circuit after mapping, consuming the same power as the original one, could be easily managed by generally-used gate-level power estimation tools. This paper also investigates the correlation coefficient method (CCM). Given the signal probabilities and the correlation coefficients between signals, the dynamic power of interconnect networks can be calculated by using CCM. It can be proved that the decoupling method and CCM draw identical results, that is to say, the decoupling method implicitly preserves correlation properties between signals and there is no accuracy loss in the decoupling process. Moreover, it is addressed that the coupling capacitors in static CMOS circuits could be decoupled and mapped into an equivalent cell containing a more complicated logic block, and the power can be obtained by the probability method for dynamic CMOS logic circuits.

Qubit Mapping Based on Tabu Search

The goal of qubit mapping is to map a logical circuit to a physical device by introducing additional gates as few as possible in an acceptable amount of time.We present an effective approach called Tabu Search Based Adjustment(TSA)algorithm to construct the mappings.It consists of two key steps:one is making use of a combined subgraph isomorphism and completion to initialize some candidate mappings,and the other is dynamically modifying the mappings by TSA.Our experiments show that,compared with state-of-the-art methods,TSA can generate mappings with a smaller number of additional gates and have better scalability for large-scale circuits.

Recent progresses of NMOS and CMOS logic functions based on two-dimensional semiconductors

Metal-oxide-semiconductor field effect transistors(MOSFET)based on two-dimensional(2D)semiconductors have attracted extensive attention owing to their excellent transport properties,atomically thin geometry,and tunable bandgaps.Besides improving the transistor performance of individual device,lots of efforts have been devoted to achieving 2D logic functions or integrated circuit towards practical application.In this review,we discussed the recent progresses of 2D-based logic circuit.We will first start with the different methods for realization of n-type metal-oxide-semiconductor(NMOS)-only(or p-type metal-oxide-semiconductor(PMOS)-only)logic circuit.Next,various device polarity control and complementary-metal-oxide-semiconductor(CMOS)approaches are summarized,including utilizing different 2D semiconductors with intrinsic complementary doping,charge transfer doping,contact engineering,and electrostatics doping.We will discuss the merits and drawbacks of each approach,and lastly conclude with a short perspective on the challenges and future developments of 2D logic circuit.

Development of Ultra-High Density Silicon Nanowire Arrays for Electronics Applications

This article reviews our recent progress on ultra-high density nanowires(NWs)array-based electronics.The superlattice nanowire pattern transfer(SNAP)method is utilized to produce aligned,ultra-high density Si NW arrays.We fi rst cover processing and materials issues related to achieving bulk-like conductivity characteristics from 1020 nm wide Si NWs.We then discuss Si NW-based fi eld-effect transistors(FETs).These NWs&NW FETs provide terrifi c building blocks for various electronic circuits with applications to memory,energy conversion,fundamental physics,logic,and others.We focus our discussion on complementary symmetry NW logic circuitry,since that provides the most demanding metrics for guiding nanofabrication.Issues such as controlling the density and spatial distribution of both p-and n-type dopants within NW arrays are discussed,as are general methods for achieving Ohmic contacts to both p-and n-type NWs.These various materials and nanofabrication advances are brought together to demonstrate energy effi cient,complementary symmetry NW logic circuits.

Two-dimensional transition metal dichalcogenides for post-silicon electronics

Rapid advancements in information technology push the explosive growth in data volume,requiring greater computing-capability logic circuits.However,conventional computing-capability improving technology,which mainly relies on increasing transistor number,encounters a significant challenge due to the weak field-effect characteristics of bulk siliconbased semiconductors.Still,the ultra-thin layered bodies of two-dimensional transition metal dichalcogenides(2D-TMDCs)materials enable excellent field-effect characteristics and multiple gate control ports,facilitating the integration of the functions of multiple transistors into one.Generally,the computing-capability improvement of the transistor cell in logic circuits will greatly alleviate the challenge in transistor numbers.In other words,one can only use a small number,or even just one,2DTMDCs-based transistors to conduct the sophisticated logic operations that have to be realized by using many traditional transistors.In this review,from material selection,device structure optimization,and circuit architecture design,we discuss the developments,challenges,and prospects for 2D-TMDCs-based logic circuits.

Design of ternary low-power Domino JKL flip-flop and its application

By researching the ternary flip-tlop and the adiabatic Domino circuit,a novel design of low-power ternary Domino JKL flip-flop on the switch level is proposed.First,the switch-level structure of the ternary adiabatic Domino JKL flip-flop is derived according to the switch-signal theory and its truth table.Then the ternary loop operation circuit and ternary reverse loop operation circuit are achieved by employing the ternary JKL tlip-tlop. Finally,the circuit is simulated by using the Spice tool and the results show that the logic function is correct. The energy consumption of the ternary adiabatic Domino JKL flip-flop is 69%less than its conventional Domino counterpart.

A Highly Selective Chemosensor for Cu^2＋ Based on a Diarylethene Linking an Aminoquinoline Unit

A new diarylethene derivative containing an aminoquinoline unit was synthesized and its structure was determined by single crystal X-ray diffraction analysis. Its properties such as photochromism, fluorescent switches and detection for metal ions were measured. The results indicated that the closed-ring of the diarylethene was highly selective toward Cu^2＋ with an obvious absorption decrease and color changes from blue to colorless, even in the presence of other metal ions. The binding constant for the closed isomer of this new diarylethene and Cu^2＋ was 2.0× 10^4 L·mol^-1 and the limit of detection for Cu^2＋ was calculated to be lower than that in drink water. Finally, a logic circuit was constructed by using the absorption intensity as the output signal with the inputs of the combina- tional stimuli of light and Cu^2＋.