Two simple voltage-controlled-oscillators (VCO) with linear tuning laws employing only a single current feedback operational amplifier (CFOA) in conjunction with two analog multipliers (AM) have been highlighted. The ...Two simple voltage-controlled-oscillators (VCO) with linear tuning laws employing only a single current feedback operational amplifier (CFOA) in conjunction with two analog multipliers (AM) have been highlighted. The workability of the presented VCOs has been demonstrated by experimental results based upon AD844 type CFOAs and AD534 type AMs.展开更多
This paper presents a 10-bit 20 MS/s pipelined Analog-to-Digital Converter(ADC)using op amp sharing approach and removing Sample and Hold Amplifier(SHA)or SHA-less technique to reach the goal of low-power consumption....This paper presents a 10-bit 20 MS/s pipelined Analog-to-Digital Converter(ADC)using op amp sharing approach and removing Sample and Hold Amplifier(SHA)or SHA-less technique to reach the goal of low-power consumption.This design was fabricated in TSMC 0.18 μm 1P6M CMOS technology.Measurement results show at supply voltage of 1.8 V,a SFDR of 42.46 dB,a SNDR of 39.45 dB,an ENOB of 6.26,and a THD of 41.82 dB are at 1 MHz sinusoidal signal input.In addition,the DNL and INL are 1.4 LSB and 3.23 LSB respectively.The power consumption is 28.8 mW.The core area is 0.595 mm2 and the chip area including pads is 1.468 mm2.展开更多
New voltage-controlled floating inductors employing CFOAs and an analog multiplier have been presented which have the attractive features of using a canonic number of passive components (only two resistors and a capac...New voltage-controlled floating inductors employing CFOAs and an analog multiplier have been presented which have the attractive features of using a canonic number of passive components (only two resistors and a capacitor) and not requiring any component-matching conditions and design constraints for the intended type of inductance realization. The workability and applications of the new circuits have been demonstrated by SPICE simulation and hardware experimental results based upon AD844-type CFOAs and AD633-type/MPY534 type analog multipliers.展开更多
Apower-efficient 12-bit40-MS/spipelineanalog-to-digitalconverter（ADC）implementedina0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire inpu...Apower-efficient 12-bit40-MS/spipelineanalog-to-digitalconverter（ADC）implementedina0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two op- amp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode （RFC） amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADC＇s performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range （SFDR） of 75.7 dB and a signal-to-noise-plus-distortion ratio （SNDR） of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity （DNL） and integral nonlinearity （INL） are -0.43 to ＋0.48 LSB and -1.62 to ＋ 1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure- of-merit （FOM） of 0.63 pJ per conversion-step.展开更多
A 10-bit 30-MS/s pipelined analog-to-digital converter（ADC） is presented.For the sake of lower power and area,the pipelined stages are scaled in current and area,and op amps are shared between the successive stages....A 10-bit 30-MS/s pipelined analog-to-digital converter（ADC） is presented.For the sake of lower power and area,the pipelined stages are scaled in current and area,and op amps are shared between the successive stages. The ADC is realized in the 0.13-μm 1-poly 8-copper mixed signal CMOS process operating at 1.2-V supply voltage. Design approaches are discussed to overcome the challenges associated with this choice of process and supply voltage, such as limited dynamic range,poor analog characteristic devices,the limited linearity of analog switches and the embedded sub-1-V bandgap voltage reference.Measured results show that the ADC achieves 55.1-dB signal-to-noise and distortion ratio,67.5-dB spurious free dynamic range and 19.2-mW power under conditions of 30 MSPS and 10.7- MHz input signal.The FoM is 0.33 pJ/step.The peak integral and differential nonlinearities are 1.13 LSB and 0.77 LSB,respectively.The ADC core area is 0.94 mm^2.展开更多
This paper presents a 12-bit 100 MS/s CMOS pipelined analog-to-digital converter （ADC） with digital background calibration. A large magnitude calibration signal is injected into the multiplying digital-to-analog con...This paper presents a 12-bit 100 MS/s CMOS pipelined analog-to-digital converter （ADC） with digital background calibration. A large magnitude calibration signal is injected into the multiplying digital-to-analog converter （MDAC） while the architecture of the MDAC remains unchanged. When sampled at 100 MS/s, it takes only 2.8 s to calibrate the 12-bit prototype ADC and achieves a peak spurious-free dynamic range of 85 dB and a peak signal-to-noise plus distortion ratio of 66 dB with 2 MHz input. Integral nonlinearity is improved from 1.9 to 0.6 least significant bits after calibration. The chip is fabricated in a 0.18μm CMOS process, occupies an active area of 2.3 × 1.6 mm^2, and consumes 205 mW at 1.8 V.展开更多
文摘Two simple voltage-controlled-oscillators (VCO) with linear tuning laws employing only a single current feedback operational amplifier (CFOA) in conjunction with two analog multipliers (AM) have been highlighted. The workability of the presented VCOs has been demonstrated by experimental results based upon AD844 type CFOAs and AD534 type AMs.
文摘以TSMC0.18μmCMOS制程实现10位元(10-bit)、每秒取样2×107次、操作电压1.8 V的管线式(pipe-line)模拟数字转换器(ADC)芯片。本设计主要是使用1.5-bit/stage架构,并且配合运算放大器(op amp)共享(sharing)技术,拔除传统第一级取样保持放大器(SHA,sample and hold amplifier)以节省功耗。此芯片的量测结果为输入信号频率2 MHz时,输出的SNDR与ENOB各为46.2 dB与7.32-bit,包含焊线垫片(pad)的芯片面积为1.54(1.391×1.107)mm2,芯片功耗为29.2 mW。
基金provided by National Chip Implementation Center(CIC)
文摘This paper presents a 10-bit 20 MS/s pipelined Analog-to-Digital Converter(ADC)using op amp sharing approach and removing Sample and Hold Amplifier(SHA)or SHA-less technique to reach the goal of low-power consumption.This design was fabricated in TSMC 0.18 μm 1P6M CMOS technology.Measurement results show at supply voltage of 1.8 V,a SFDR of 42.46 dB,a SNDR of 39.45 dB,an ENOB of 6.26,and a THD of 41.82 dB are at 1 MHz sinusoidal signal input.In addition,the DNL and INL are 1.4 LSB and 3.23 LSB respectively.The power consumption is 28.8 mW.The core area is 0.595 mm2 and the chip area including pads is 1.468 mm2.
文摘New voltage-controlled floating inductors employing CFOAs and an analog multiplier have been presented which have the attractive features of using a canonic number of passive components (only two resistors and a capacitor) and not requiring any component-matching conditions and design constraints for the intended type of inductance realization. The workability and applications of the new circuits have been demonstrated by SPICE simulation and hardware experimental results based upon AD844-type CFOAs and AD633-type/MPY534 type analog multipliers.
文摘提出了一种新型的基于运算放大器的开关电容采样保持电路结构.采用速度补偿解决了高速高分辨采样保持电路对放大器要求增益高和速度快之间的矛盾.具体设计了采样保持电路,特别设计了其中的快速时间连续电压比较器.用Chart0.35μmCMOS工艺,进行HSPICE仿真,结果表明,本文设计的采样保持电路的分辨率为10位,采样速率高于70MHz s.
基金Project supported by the National Science and Technology Major Projects of China(No.2012ZX03001018-001)the Fundamental Research Funds for the Central Universities,China(No.K50511250006)
文摘Apower-efficient 12-bit40-MS/spipelineanalog-to-digitalconverter（ADC）implementedina0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two op- amp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode （RFC） amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADC＇s performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range （SFDR） of 75.7 dB and a signal-to-noise-plus-distortion ratio （SNDR） of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity （DNL） and integral nonlinearity （INL） are -0.43 to ＋0.48 LSB and -1.62 to ＋ 1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure- of-merit （FOM） of 0.63 pJ per conversion-step.
基金supported by the National High Technology Research and Development Program of China(No.2009AA011600)the Project for Young Scientists Fund of Fudan University,China(No.09FQ33)the State Key Laboratory ASIC & System(Fudan University), China(No.09MS008)
文摘A 10-bit 30-MS/s pipelined analog-to-digital converter（ADC） is presented.For the sake of lower power and area,the pipelined stages are scaled in current and area,and op amps are shared between the successive stages. The ADC is realized in the 0.13-μm 1-poly 8-copper mixed signal CMOS process operating at 1.2-V supply voltage. Design approaches are discussed to overcome the challenges associated with this choice of process and supply voltage, such as limited dynamic range,poor analog characteristic devices,the limited linearity of analog switches and the embedded sub-1-V bandgap voltage reference.Measured results show that the ADC achieves 55.1-dB signal-to-noise and distortion ratio,67.5-dB spurious free dynamic range and 19.2-mW power under conditions of 30 MSPS and 10.7- MHz input signal.The FoM is 0.33 pJ/step.The peak integral and differential nonlinearities are 1.13 LSB and 0.77 LSB,respectively.The ADC core area is 0.94 mm^2.
文摘This paper presents a 12-bit 100 MS/s CMOS pipelined analog-to-digital converter （ADC） with digital background calibration. A large magnitude calibration signal is injected into the multiplying digital-to-analog converter （MDAC） while the architecture of the MDAC remains unchanged. When sampled at 100 MS/s, it takes only 2.8 s to calibrate the 12-bit prototype ADC and achieves a peak spurious-free dynamic range of 85 dB and a peak signal-to-noise plus distortion ratio of 66 dB with 2 MHz input. Integral nonlinearity is improved from 1.9 to 0.6 least significant bits after calibration. The chip is fabricated in a 0.18μm CMOS process, occupies an active area of 2.3 × 1.6 mm^2, and consumes 205 mW at 1.8 V.
