Using composite field arithmetic in Galois field can result in the compact Rijndael S-Box. However, the power con- sumption of this solution is too large to be used in resource-limited embedded systems. A full-custom ...Using composite field arithmetic in Galois field can result in the compact Rijndael S-Box. However, the power con- sumption of this solution is too large to be used in resource-limited embedded systems. A full-custom hardware implementation of composite field S-Box is proposed for these targeted domains in this paper. The minimization of power consumption is implemented by optimizing the architecture of the composite field S-Box and using the pass transmission gate (PTG) to realize the logic functions of S-Box. Power simulations were performed using the netlist extracted from the layout. HSPICE simulation results indicated that the proposed S-Box achieves low power consumption of about 130 μW at 10 MHz using 0.25 μm/2.5 V technology, while the consumptions of the positive polarity reed-muller (PPRM) based S-Box and composite field S-Box based on the conventional CMOS logic style are about 240 μW and 420 μW, respectively. The simulations also showed that the presented S-Box obtains better low-voltage operating property, which is clearly relevant for applications like sensor nodes, smart cards and radio frequency identification (RFID) tags.展开更多
This paper highlights the memristor bridge-based lowpass filter (LPF) and improved image processing algorithms along with a novel adaptive Gaussian filter for denoising image and a new Gaussian pyramid for scale invar...This paper highlights the memristor bridge-based lowpass filter (LPF) and improved image processing algorithms along with a novel adaptive Gaussian filter for denoising image and a new Gaussian pyramid for scale invariant feature transform (SIFT). First, a novel kind of LPF based on the memristor bridge is designed, whose cut-off frequency and other traits are demonstrated to change with different time and memristance. In light of the changeable parameter of the memristor bridge-based LPF, a new adaptive Gaussian filter and an improved SIFT algorithm are presented. Finally, experiment results show that the peak signalto- noise ratio (PSNR) of our denoising is bettered more than 2.77 dB compared to the corresponding of the traditional Gaussian filter, and our improved SIFT performances including the number of matched feature points and the percent of correct matches are higher than the traditional SIFT, which verifies feasibility and effectiveness of our algorithm.展开更多
An effective technique to design compact low pass filter has been proposed in this paper. The proposed method is highly effective for L-band applications. Low impedance microstrip lines are arranged such that they wor...An effective technique to design compact low pass filter has been proposed in this paper. The proposed method is highly effective for L-band applications. Low impedance microstrip lines are arranged such that they work as open stubs to increase the selectivity of the filter. Using the proposed technique about 57% size reduction has been realized with sharper roll off characteristics. An empirical expression is derived to determine the dimension of resonators. For cut-off frequency of 1.7 GHz the investigated method has been fabricated and tested. There is a close agreement be-tween simulated and measured展开更多
This paper presents a novel low-pass filter （LPF） with sharp rejection, wide stopband and compact size, which are realized by the defected ground structure （DGS） and the defected microstrip structure （DMS）. The ...This paper presents a novel low-pass filter （LPF） with sharp rejection, wide stopband and compact size, which are realized by the defected ground structure （DGS） and the defected microstrip structure （DMS）. The equivalent circuit model is proposed and the circuit parameters are extracted by the circuit simulation software. The parameters measured are 3 dB cutoff frequency fc of 5.2 GHz, the insertion loss less than 0.5 dB from DC to 4.0 GHz and S21 less than -20 dB within the wide stopband from 6 GHz to 16 GHz. The results of the circuit optimization agree well with those of the full wave simulation and the measured ones, which validate the effectiveness of the equivalent circuit model. The size of the proposed LPF is decreased compared with normal LPF. This LPF can be applied in rectennas to eliminate high order harmonics.展开更多
Digital filters play a key role in the field of digital signal processing. This paper presents a linear phase digital low pass finite impulse response (FIR) filter design using particle swarm optimization and its two ...Digital filters play a key role in the field of digital signal processing. This paper presents a linear phase digital low pass finite impulse response (FIR) filter design using particle swarm optimization and its two new variants, dynamic and adjustable particle swarm optimization (DAPSO) and particle swarm optimization with variable acceleration factor (PSO-VAF) and illustrates the superiority of the PSO-VAF method over PSO based methods. Two fitness functions are considered. The fitness1 is used to find the possible minimum ripples in pass band and stop band in case of PSO, DAPSO and PSO-VAF. Fitness2 is able to control the ripples in both bands separately. A comparison of simulation results demonstrates the performance of PSO and its methods in designing digital low pass FIR filters.展开更多
In this paper the design and implementation of sixth-order lowpass elliptic switched-capacitor filter( SCF) for interface circuit of Micro-Electro-Mechanical System( MEMS) sensor are presented. This work aims to lower...In this paper the design and implementation of sixth-order lowpass elliptic switched-capacitor filter( SCF) for interface circuit of Micro-Electro-Mechanical System( MEMS) sensor are presented. This work aims to lower total harmonic distortion( THD) without deteriorating other performances. After system design in Simulink,the filter is realized in transistor level and finally fabricated in Central Semiconductor Manufacturing Corporation( CSMC) 0.5 μm metal-oxide-semiconductor( CMOS) technology. Typical measured results are: it operates with 25: 1 clock-to-corner frequency ratio and a 10 k Hz maximum corner frequency. The maximum passband ripple is about 0.49 d B and the minimum stopband rejection is 40 d B for the temperature from-20 ℃to 80 ℃. For the 250 k Hz clock frequency setting,given the 1 k Hz,- 8 d BVrms input signal,the measured worst case THD is-64 d B. The active area of the chip is 2.8 mm2 with 8 pads. The analog power dissipation is10 m W from a 5 V power supply.展开更多
A novel defected ground structure （DGS） for the microstrip line is proposed in this paper. The DGS lattice has more defect parameters so that it can provide better performance than the conventional dumbbell-shaped D...A novel defected ground structure （DGS） for the microstrip line is proposed in this paper. The DGS lattice has more defect parameters so that it can provide better performance than the conventional dumbbell-shaped DGS. Selectivity is improved by 97.2% with a sharpness factor of 24.6%. The method is applied to the design of a low-pass filter to confirm validity of the proposed DGS.展开更多
It is a time-consuming and often iterative procedure to determine design parameters based on fine, accurate but expensive, models. To decrease the number of fine model evaluations, space mapping techniques may be empl...It is a time-consuming and often iterative procedure to determine design parameters based on fine, accurate but expensive, models. To decrease the number of fine model evaluations, space mapping techniques may be employed. In this approach, it is assumed both fine model and coarse, fast but inaccurate, one are available. First, the coarse model is optimized to obtain design parameters satisfying design objectives. Next, auxiliary parameters are calibrated to match coarse and fine models’ responses. Then, the improved coarse model is re-optimized to obtain new design parameters. The design procedure is stopped when a satisfactory solution is reached. In this paper, an implicit space mapping method is used to design a microstrip low-pass elliptic filter. Simulation results show that only two fine model evaluations are sufficient to get satisfactory results.展开更多
Complimentary hexagonal-omega structures are used to design compact, low insertion loss (IL), low pass filter with sharp cut-off. It has been designed for improvement of roll-off performance based on both μ and ε ne...Complimentary hexagonal-omega structures are used to design compact, low insertion loss (IL), low pass filter with sharp cut-off. It has been designed for improvement of roll-off performance based on both μ and ε negative property of the complimentary hex-omega structure while maintaining the filter pass-band performance. By properly designing and loading the hexagonal-omega structure in the ground of microstrip line not only improve the roll-off of the low pass filter, but also reduced the filter size. The simulated results indicate that the proposed filter achieves a flat pass band with no ripples as well as selectivity of 19.68 dB/GHz, corresponding to 5-unit cells hex-omega structures. This significantly exceeds the 5.6 dB/GHz selectivity of the conventional low pass filter design, due to sub-lambda dimensions of the hex-omega structure. A prototype filter implementing area is: 0.712λg x 0.263λg, λg being the guided wavelength at 3-dB cut-off frequency (fc). The proposed filter has a size smaller by 36.2%.展开更多
A new low power quasi adiabatic logic,complementary pass transistor adiabatic logic (CPAL),is presented.The CPAL circuit is driven by a new three phase power clock,and its non adiabatic loss on output loads can b...A new low power quasi adiabatic logic,complementary pass transistor adiabatic logic (CPAL),is presented.The CPAL circuit is driven by a new three phase power clock,and its non adiabatic loss on output loads can be effectively reduced by using complementary pass transistor logic and transmission gates.Furthermore,the minimization of the energy consumption can be obtained by choosing the optimal size of bootstrapped nMOS transistors,thus it has more efficient energy transfer and recovery.A three phase power supply generator with a small control logic circuit and a single inductor is proposed.An 8 bit adder based on CPAL is designed and verified.With MOSIS 0 25μm CMOS technology,the CPAL adder consumes only 35% of the dissipated energy of a 2N 2N2P adder and is about 50% of the dissipated energy of a PFAL adder for clock rates ranging from 50 to 200MHz.展开更多
基金Project supported by the Hi-Tech Research and Development Program (863) of China (No. 2006AA01Z226)the Scientific Research Foundation of Huazhong University of Science and Technol-ogy (No. 2006Z001B), China
文摘Using composite field arithmetic in Galois field can result in the compact Rijndael S-Box. However, the power con- sumption of this solution is too large to be used in resource-limited embedded systems. A full-custom hardware implementation of composite field S-Box is proposed for these targeted domains in this paper. The minimization of power consumption is implemented by optimizing the architecture of the composite field S-Box and using the pass transmission gate (PTG) to realize the logic functions of S-Box. Power simulations were performed using the netlist extracted from the layout. HSPICE simulation results indicated that the proposed S-Box achieves low power consumption of about 130 μW at 10 MHz using 0.25 μm/2.5 V technology, while the consumptions of the positive polarity reed-muller (PPRM) based S-Box and composite field S-Box based on the conventional CMOS logic style are about 240 μW and 420 μW, respectively. The simulations also showed that the presented S-Box obtains better low-voltage operating property, which is clearly relevant for applications like sensor nodes, smart cards and radio frequency identification (RFID) tags.
基金supported by the National Natural Science Foundation of China(61550110248)
文摘This paper highlights the memristor bridge-based lowpass filter (LPF) and improved image processing algorithms along with a novel adaptive Gaussian filter for denoising image and a new Gaussian pyramid for scale invariant feature transform (SIFT). First, a novel kind of LPF based on the memristor bridge is designed, whose cut-off frequency and other traits are demonstrated to change with different time and memristance. In light of the changeable parameter of the memristor bridge-based LPF, a new adaptive Gaussian filter and an improved SIFT algorithm are presented. Finally, experiment results show that the peak signalto- noise ratio (PSNR) of our denoising is bettered more than 2.77 dB compared to the corresponding of the traditional Gaussian filter, and our improved SIFT performances including the number of matched feature points and the percent of correct matches are higher than the traditional SIFT, which verifies feasibility and effectiveness of our algorithm.
文摘An effective technique to design compact low pass filter has been proposed in this paper. The proposed method is highly effective for L-band applications. Low impedance microstrip lines are arranged such that they work as open stubs to increase the selectivity of the filter. Using the proposed technique about 57% size reduction has been realized with sharper roll off characteristics. An empirical expression is derived to determine the dimension of resonators. For cut-off frequency of 1.7 GHz the investigated method has been fabricated and tested. There is a close agreement be-tween simulated and measured
文摘This paper presents a novel low-pass filter （LPF） with sharp rejection, wide stopband and compact size, which are realized by the defected ground structure （DGS） and the defected microstrip structure （DMS）. The equivalent circuit model is proposed and the circuit parameters are extracted by the circuit simulation software. The parameters measured are 3 dB cutoff frequency fc of 5.2 GHz, the insertion loss less than 0.5 dB from DC to 4.0 GHz and S21 less than -20 dB within the wide stopband from 6 GHz to 16 GHz. The results of the circuit optimization agree well with those of the full wave simulation and the measured ones, which validate the effectiveness of the equivalent circuit model. The size of the proposed LPF is decreased compared with normal LPF. This LPF can be applied in rectennas to eliminate high order harmonics.
文摘Digital filters play a key role in the field of digital signal processing. This paper presents a linear phase digital low pass finite impulse response (FIR) filter design using particle swarm optimization and its two new variants, dynamic and adjustable particle swarm optimization (DAPSO) and particle swarm optimization with variable acceleration factor (PSO-VAF) and illustrates the superiority of the PSO-VAF method over PSO based methods. Two fitness functions are considered. The fitness1 is used to find the possible minimum ripples in pass band and stop band in case of PSO, DAPSO and PSO-VAF. Fitness2 is able to control the ripples in both bands separately. A comparison of simulation results demonstrates the performance of PSO and its methods in designing digital low pass FIR filters.
基金Sponsored by the Fundamental Research Funds for the Central Universities(Grant No.HIT.NSRIF.2013040)
文摘In this paper the design and implementation of sixth-order lowpass elliptic switched-capacitor filter( SCF) for interface circuit of Micro-Electro-Mechanical System( MEMS) sensor are presented. This work aims to lower total harmonic distortion( THD) without deteriorating other performances. After system design in Simulink,the filter is realized in transistor level and finally fabricated in Central Semiconductor Manufacturing Corporation( CSMC) 0.5 μm metal-oxide-semiconductor( CMOS) technology. Typical measured results are: it operates with 25: 1 clock-to-corner frequency ratio and a 10 k Hz maximum corner frequency. The maximum passband ripple is about 0.49 d B and the minimum stopband rejection is 40 d B for the temperature from-20 ℃to 80 ℃. For the 250 k Hz clock frequency setting,given the 1 k Hz,- 8 d BVrms input signal,the measured worst case THD is-64 d B. The active area of the chip is 2.8 mm2 with 8 pads. The analog power dissipation is10 m W from a 5 V power supply.
基金Project supported by the Shanghai Leading Academic Discipline Project (Grant No.T0102)
文摘A novel defected ground structure （DGS） for the microstrip line is proposed in this paper. The DGS lattice has more defect parameters so that it can provide better performance than the conventional dumbbell-shaped DGS. Selectivity is improved by 97.2% with a sharpness factor of 24.6%. The method is applied to the design of a low-pass filter to confirm validity of the proposed DGS.
文摘It is a time-consuming and often iterative procedure to determine design parameters based on fine, accurate but expensive, models. To decrease the number of fine model evaluations, space mapping techniques may be employed. In this approach, it is assumed both fine model and coarse, fast but inaccurate, one are available. First, the coarse model is optimized to obtain design parameters satisfying design objectives. Next, auxiliary parameters are calibrated to match coarse and fine models’ responses. Then, the improved coarse model is re-optimized to obtain new design parameters. The design procedure is stopped when a satisfactory solution is reached. In this paper, an implicit space mapping method is used to design a microstrip low-pass elliptic filter. Simulation results show that only two fine model evaluations are sufficient to get satisfactory results.
文摘Complimentary hexagonal-omega structures are used to design compact, low insertion loss (IL), low pass filter with sharp cut-off. It has been designed for improvement of roll-off performance based on both μ and ε negative property of the complimentary hex-omega structure while maintaining the filter pass-band performance. By properly designing and loading the hexagonal-omega structure in the ground of microstrip line not only improve the roll-off of the low pass filter, but also reduced the filter size. The simulated results indicate that the proposed filter achieves a flat pass band with no ripples as well as selectivity of 19.68 dB/GHz, corresponding to 5-unit cells hex-omega structures. This significantly exceeds the 5.6 dB/GHz selectivity of the conventional low pass filter design, due to sub-lambda dimensions of the hex-omega structure. A prototype filter implementing area is: 0.712λg x 0.263λg, λg being the guided wavelength at 3-dB cut-off frequency (fc). The proposed filter has a size smaller by 36.2%.
文摘A new low power quasi adiabatic logic,complementary pass transistor adiabatic logic (CPAL),is presented.The CPAL circuit is driven by a new three phase power clock,and its non adiabatic loss on output loads can be effectively reduced by using complementary pass transistor logic and transmission gates.Furthermore,the minimization of the energy consumption can be obtained by choosing the optimal size of bootstrapped nMOS transistors,thus it has more efficient energy transfer and recovery.A three phase power supply generator with a small control logic circuit and a single inductor is proposed.An 8 bit adder based on CPAL is designed and verified.With MOSIS 0 25μm CMOS technology,the CPAL adder consumes only 35% of the dissipated energy of a 2N 2N2P adder and is about 50% of the dissipated energy of a PFAL adder for clock rates ranging from 50 to 200MHz.
