A Δ ∑ fractional-N frequency synthesizer for FM tuner using low noise filter and quantization noise suppression technique

A △∑ fractional-N frequency synthesizer fabricated in a 130 nm CMOS technology is presented for the application of an FM tuner. A low noise filter, occupying a small die area and decreasing the output noise, is integrated on a chip. A quantization noise suppression technique, using a reduced step size of the frequency divider, is also adopted. The proposed synthesizer needs no off-chip components and occupies an area of 0.7 mm2. The in-band phase noise （from 10 to 100 kHz） below -108 dBc/Hz and out-of-band phase noise of -122.9 dBc/Hz （at 1 MHz offset） are measured with a loop bandwidth of 200 kHz. The quantization noise suppression technique reduces the in-band and out-of band phase noise by 15 dB and 7 dB respectively. The integrated RMS phase error is no more than 0.48°. The proposed synthesizer consumes a total power of 7.4 mW and the frequency resolution is less than 1 Hz.

A 55 nm CMOS ΔΣ fractional-N frequency synthesizer for WLAN transceivers with low noise filters

A fully integrated △∑ fractional-N frequency synthesizer fabricated in a 55 nm CMOS technology is presented for the application of IEEE 802.11b/g wireless local area network （WLAN） transceivers. A low noise filter, occupying a small die area, whose power supply is given by a high PSRR and low noise LDO regulator, is integrated on chip. The proposed synthesizer needs no off-chip components and occupies an area of 0.72 mm^2excluding PAD. Measurement results show that in all channels, the phase noise of the synthesizer achieves -99 dBc/Hz and -119 dBc/Hz in band and out of band respectively with a reference frequency of 40 MHz and a loop bandwidth of 200 kHz. The integrated RMS phase error is no more than 0.6°. The proposed synthesizer consumes a total power of 15.6 mW.

Design of low noise class D amplifiers using an integrated filter

This paper investigates the noise sources in a single-ended class D amplifier（SECDA） and suggests corresponding ways to lower the noise.The total output noise could be expressed as a function of the gain and noises from different sources.According to the function,the bias voltage（V_B） is a primary noise source,especially for a SECDA with a large gain.A low noise SECDA is obtained by integrating a filter into the SECDA to lower the noise of the V_B.The filter utilizes an active resister and an 80 pF capacitance to get a 3 Hz pole.A noise test and fast Fourier transform analysis show that the noise performance of this SECDA is the same as that of a SECDA with an external filter.

A low-noise widely tunable Gm-C filter with frequency calibration

A fourth-order Gm-C Chebyshev low-pass filter is presented as channel selection filter for reconfigurable multi-mode wireless receivers. Low-noise technologies are proposed in optimizing the noise characteristics of both the Gm cells and the filter topology. A frequency tuning strategy is used by tuning both the transconductance of the Gm cells and the capacitance of the capacitor banks. To achieve accurate cut-off frequencies, an on-chip calibration circuit is presented to compensate for the frequency inaccuracy introduced by process variation. The filter is fabricated in a 0.13 m CMOS process. It exhibits a wide programmable bandwidth from 322.5 k Hz to20 MHz. Measured results show that the filter has low input referred noise of 5.9 n V/（Hz）^（1/2） and high out-of-band IIP3 of 16.2 d Bm. It consumes 4.2 and 9.5 m W from a 1 V power supply at its lowest and highest cut-off frequencies respectively.

A low power 2.4 GHz transceiver for ZigBee applications

This paper presents a low power 2.4 GHz transceiver for ZigBee applications.This transceiver adopts low power system architecture with a low-IF receiver and a direct-conversion transmitter.The receiver consists of a new low noise amplifier（LNA） with a noise cancellation function,a new inverter-based variable gain complex filter （VGCF） for image rejection,a passive quadrature mixer,and a decibel linear programmable gain amplifier（PGA）. The transmitter adopts a quadrature mixer and a class-B mode variable gain power amplifier（PA） to reduce power consumption.This transceiver is implemented in 0.18μm CMOS technology.The receiver achieves—95 dBm of sensitivity,28 dBc of image rejection,and -8 dBm of third-order input intercept point（IIP3）.The transmitter can deliver a maximum of＋3 dBm output power with PA efficiency of 30%.The whole chip area is less than 4.32 mm^2. It only consumes 12.63 mW in receiving mode and 14.22 mW in transmitting mode,respectively.