Low power consumption 4-channel variable optical attenuator array based on planar lightwave circuit technique

The power consumption of a variable optical attenuator（VOA） array based on a silica planar lightwave circuit was investigated. The thermal field profile of the device was optimized using the finite-element analysis. The simulation results showed that the power consumption reduces as the depth of the heat-insulating grooves is deeper, the up-cladding is thinner,the down-cladding is thicker, and the width of the cladding ridge is narrower. The materials component and thickness of the electrodes were also optimized to guarantee the driving voltage under 5 V. The power consumption was successfully reduced to as low as 155 mW at an attenuation of 30 dB in the experiment.

SYNCHRONOUS DERIVED CLOCK AND SYNTHESIS OF LOW POWER SEQUENTIAL CIRCUITS

Based on analyzing significance of controlling clock in design of low power sequential circuits, this paper proposes a technique that the gating signal is derived from the master latch in a flip-flop to make the derived clock having no glitch and no skew. The design of a decimal counter with half-frequency division shows that by using the synchronous derived clock the counter has lower power dissipation as well as simpler combinational logic. Computer simulation shows 20% power saving.

Ultra-Low Power Pipeline Structure Exploiting Noncritical Stage with Circuit-Level Timing Speculation

With the increase of the clock frequency and silicon integration, power aware computing has become a critical concern in the design of the embedded processor and system-on-chip （SoC）. Dynamic voltage scaling （DVS） is an effective method for low-power designs. However, traditional DVS methods have two deficiencies. First, they have a conservative safety margin which is not necessary for most of the time. Second, they are exclusively concerned with the critical stage and ignore the significant potential free slack time of the noncritical stage. These factors lead to a large amount of power waste. In this paper, a novel pipeline structure with ultra-low power consumption is proposed. It cuts off the safety margin and takes use of the noncritical stages at the same time. A prototype pipeline is designed in 0.13 μm technology and analyzed. The result shows that a large amount of energy can be saved by using this structure. Compared with the fixed voltage case, 50% of the energy can be saved, and with respect to the traditional adaptive voltage scaling design, 37.8% of the energy can be saved.

A Low Power Non-Volatile LR-WPAN Baseband Processor with Wake-Up Identification Receiver

The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power management module.The main receiver adopts a unified simplified synchronization method and channel codec with proactive Reed-Solomon Bypass technique,which increases the robustness and energy efficiency of receiver.The WUI receiver specifies the communication node and wakes up the transceiver to reduce average power consumption of the transceiver.The embedded NVM can backup/restore the states information of processor that avoids the loss of the state information caused by power failure and reduces the unnecessary power of repetitive computation when the processor is waked up from power down mode.The baseband processor is designed and verified on a FPGA board.The simulated power consumption of processor is 5.1uW for transmitting and 28.2μW for receiving.The WUI receiver technique reduces the average power consumption of transceiver remarkably.If the transceiver operates 30 seconds in every 15 minutes,the average power consumption of the transceiver can be reduced by two orders of magnitude.The NVM avoids the loss of the state information caused by power failure and energy waste caused by repetitive computation.

Design of low-offset low-power CMOS amplifier for biosensor application

A compacted and low-offset low-power CMOS am- plifier for biosensor application is presented in this paper. It includes a low offset Op-Amp and a high precision current reference. With a novel continuous-time DC offset rejection scheme, the IC achieves lower offset voltage and lower power consumption compared to previous designs. This configuration rejects large DC offset and drift that exist at the skin-electrode interface without the need of external components. The proposed amplifier has been implemented in SMIC 0.18-μm 1P6M CMOS technol-ogy, with an active silicon area of 100 μm by 120 μm. The back-annotated simulation results demonstrated the circuit features the systematic offset voltage less than 80 μV, the offset drift about 0.27 μV/℃ for temperature ranging from –30℃ to 100℃ and the total power dissipation consumed as low as 37.8 μW from a 1.8 V single supply. It dedicated to monitor low amplitude biomedical signals recording.

Leakage Reduction Using DTSCL and Current Mirror SCL Logic Structures for LP-LV Circuits

This paper presents a novel approach to design robust Source Coupled Logic (SCL) for implementing ultra low power circuits. In this paper, we propose two different source coupled logic structures and analyze the performance of these structures with STSCL (Sub-threshold SCL). The first design under consideration is DTPMOS as load device which analyses the performance of Dynamic Threshold SCL (DTSCL) Logic with previous source coupled logic for ultra low power operation. DTSCL circuits exhibit a better power-delay Performance compared with the STSCL Logic. It can be seen that the proposed circuit provides 56% reduction in power delay product. The second design under consideration uses basic current mirror active load device to provide required voltage swing. Current mirror source coupled logic (CMSCL) can be used for high speed operation. The advantage of this design is that it provides 54% reduction in power delay product over conventional STSCL. The main drawback of this design is that it provides a higher power dissipation compared to other source coupled logic structures. The proposed circuit provides lower sensitivity to temperature and power supply variation, with a superior control over power dissipation. Measurements of test structures simulated in 0.18 μm CMOS technology shows that the proposed DTSCL logic concept can be utilized successfully for bias currents as low as 1 pA. Measurements show that existing standard cell libraries offer a good solution for ultra low power SCL circuits. Cadence Virtuoso schematic editor and Spectre Simulation tools have been used.

A novel low-swing interconnect optimization model with delay and bandwidth constraints

Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits. Based on the RLC interconnect delay model, by wire sizing, wire spacing arid adopting low-swing interconnect technology, this paper proposed a power-area optimization model considering delay and bandwidth constraints simultaneously. The optimized model is verified based on 65-am and 90-nm complementary metal-oxide semiconductor （CMOS） interconnect parameters. The verified results show that averages of 36% of interconnect power and 26% of repeater area can be saved under 65-nm CMOS process. The proposed model is especially suitable for the computer-aided design of nanometer scale systems-on-chip.

Design and Analysis of a Power Efficient Linearly Tunable Cross-Coupled Transconductor Having Separate Bias Control

A common current source, generally used to bias cross-coupled differential amplifiers in a transconductor, controls third harmonic distortion (HD3) poorly. Separate current sources are shown to provide better control on HD3) . In this paper, a detailed design and analysis is presented for a transconductor made using this biasing technique. The transconductor, in addition, is made to offer high Gm, low power dissipation and is designed for linearly tunable Gm with current mode load as one of the applications. The circuit exhibits HD3) of less than –43.7 dB, high current efficiency of 1.18 V-1 and Gm of 390 μS at 1 VGp-p @ 50 MHz. UMC 0.18 μm CMOS process technology is used for simulation at supply voltage of 1.8 V.

Performance Prospects of Fully-Depleted SOI MOSFET-Based Diodes Applied to Schenkel Circuit for RF-ID Chips

The feasibility of using the SOI-MOSFET as a quasi-diode to replace the Schottky-barrier diode in the Schenkel circuit is examined by device simulations primarily and experiments partly. Practical expressions of boost-up efficiency for d. c. condition and a. c. condition are proposed and are examined by simulations. It is shown that the SOI-MOSFET-based quasi-diode is a promising device for the Schenkel circuit because high boost-up efficiency can be gained easily. An a. c. analysis indicates that the fully-depleted condition should hold to suppress the floating-body effect for GHz-level RF applications of a quasi-diode.

基于先进工艺的低功耗模拟集成电路设计

阐述先进工艺的低功耗模拟集成电路设计,探讨模拟集成电路的基础知识,低功耗设计原理以及先进工艺技术的应用,分析一个高效、精密的模拟电路设计案例。

考虑低电压穿越全过程控制策略切换的双馈风机电气量研究

双馈感应发电机(doubly fed induction generator,DFIG)的电气特性在低电压穿越(low voltage ride through,LVRT)全过程均易受电网电压变化影响,而现有研究多关注故障期间DFIG的电气特性,未考虑故障清除后不同情形下DFIG电气特性的差异,且较少研究LVRT全过程DFIG的功率特性,LVRT全过程电气特性分析尚不全面。为此研究了LVRT全过程DFIG的运行状态,在故障清除前,将LVRT全过程分为故障发生、无功功率优先控制启动两个阶段,故障清除后分为撬棒二次投入、有功功率爬坡恢复两种情形进行分析。在此基础上,推导了LVRT全过程定子侧输出电流、功率的表达式,并在PSCAD中建立了DFIG仿真模型,时域仿真结果与解析表达式波形可较好吻合,证明了所提方法的有效性。

集成有源开关电感和Y源倍压单元的高增益DC-DC变换器

针对光伏发电系统中光伏组件电压等级的提升,提出一种集成有源开关电感和Y源倍压单元的高增益DC-DC变换器。所提变换器能够实现低开关管电压应力,具有高自由度电压调节能力,在满足一定升压条件下仍能保证电路的效率,在光伏发电中具有较大的应用潜力。对变换器的工作模态、器件电压电流应力、参数设计和损耗效率进行详细阐述。最后通过实验验证所提拓扑结构的可行性。

一种基于电容充放电的低功耗时钟发生器

基于SMIC 0.18μm CMOS工艺,设计了一种基于电容充放电的新型低功耗时钟发生器。为了减小温度变化引起的频率波动,设计了负温度系数偏置电路。采用了传统的占空比调节电路,可调节振荡波形的占空比。仿真结果显示,在3.3 V电源电压下,该振荡器可以稳定输出7.16 MHz频率的信号,相位噪声为-104.4 dBc/Hz,系统功耗为1.411 mW,其中环形振荡器功耗为0.811 mW。在-40℃~110℃温度变化范围内,振荡器的频率变化为7.116~7.191 MHz,容差在1.05%以内。同其他时钟发生器相比,该电路具有结构简单、功耗低,以及在宽温度范围内具有较高的频率稳定性等显著特点,能够满足芯片的工作要求,为芯片提供稳定时钟。

节点仪器采集电路低功耗设计技术探讨

近年来,随着高精度勘探技术的逐步规模化应用,无论单个项目投入设备数量,还是应用项目比例,节点仪器都呈现出增长的趋势。本文在介绍节点仪器产品现状的基础上,分析了其采集电路组成及工作功耗的主要影响因素。最后,从关键器件选型、硬件电路、固件低功耗优化设计等方面阐述了节点仪器采集电路的低功耗设计思路,并给出具体的验证实例,以期为今后体积小、重量轻、续航时间长、综合技术性能更优的节点仪器研发、制造提供参考。

太赫兹固态通信系统技术发展现状与挑战

太赫兹固态通信系统被认为是下一代通信的重要技术备选方案,其高速、实时、大容量传输特性为“万物智联”提供了可能。当前,太赫兹固态通信系统面临诸多技术挑战。为进一步推动太赫兹固态通信系统研制,梳理了太赫兹波段信号调制、固态器件、天线以及收发系统的研究进展与关键技术,并剖析了太赫兹通信系统未来的发展方向。太赫兹固态通信系统将进一步加快通信系统小型化研究,促进信号、器件、芯片、系统等多项技术深度优化融合,为商业化应用提供技术基础。

Low power mapping for AND/XOR circuits and its application in searching the best mixed-polarity

A low power mapping algorithm for technology independent AND/XOR circuits is proposed. In this algorithm, the average power of the static mixed-polarity Reed-Muller （MPRM） circuits is minimized by generating a two-input gates circuit to optimize the switching active of nodes, and the power and area of MPRM circuits are estimated by using gates from a given library. On the basis of obtaining an optimal power MPRM circuit, the best mixed-polarity is found by combining an exhaustive searching method with polarity conversion algorithms. Our experiments over 18 benchmark circuits show that compared to the power optimization for fixed-polarity Reed-Muller circuits and AND/OR circuits, power saving is up to 44.22% and 60.09%, and area saving is up to 14.13% and 32.72%, respectively.

基于0.18μm CMOS工艺的低温漂低功耗延时电路

基于0.18μm CMOS工艺设计了一款低温漂延时电路,适用于不能使用锁相环电路又对信号传输精度有要求的低功耗传感检测应用。采用正温度系数的偏置电压,通过电流镜为延时电路提供一个正温度系数的偏置电流,利用偏置电流约束电路的延时温漂,实现温漂粗调。采用数字时间转换器,通过外部输入配置,对粗调后的延时进行动态细调,使得延时电路具有更高的动态稳定性和更低的温漂特性。电路测试结果表明,在3.3 V的电源电压下,-55~125℃内延时电路的温度系数为125×10^(-6)/℃,静态功耗仅为0.72 mW。

A high efficiency charge pump circuit for low power applications

A high efficiency charge pump circuit is designed and realized. The charge transfer switch is biased by the additional capacitor and transistor to eliminate the influence of the threshold voltage. Moreover, the bulk of the switch transistor is dynamically biased so that the threshold voltage gets lower when it is turned on during charge transfer and gets higher when it is turned off. As a result, the efficiency of the charge pump circuit can be improved. A test chip has been implemented in a 0.18μm 3.3 V standard CMOS process. The measured output voltage of the eight-pumpingstage charge pump is 9.8 V with each pumping capacitor of 0.5 pF at an output current of 0.18 μA, when the clock frequency is 780 kHz and the supply voltage is 2 V. The charge pump and the clock driver consume a total current of 2.9 μA from the power supply. This circuit is suitable for low power applications.

可由异步时钟驱动的高可靠性低功耗WDT

看门狗定时器(WDT)已成为当前MCU系统中不可缺少的一部分。但随着MCU系统功能的增加,对于传统的WDT,由于其不能对异步驱动时钟进行处理或不能在低功耗模式下(系统时钟及外设时钟停止)运行,已经不适用于部分功能复杂的MCU。设计的WDT定时器对异步输入时钟及其衍生信号进行了优化,从而使其可由同步或异步时钟进行驱动,并能在低功耗模式下运行。

一种低功耗宽摆幅的绝对值电路设计

提出了一种低功耗宽摆幅的绝对值电路。该电路通过比较器输出结果判断输入电压的正负,正值利用负反馈进行保持,负值利用电压-电流转换电路和电流镜转换为正值。与传统利用二极管的设计相比,该电路避免了线性度差、功耗高的问题。基于55 nm CMOS工艺进行了电路设计,仿真结果表明,在电源电压为-1.2 V和1.2 V的条件下,电压输入摆幅高达-400~400 mV,绝对值电路误差在0.5%以内,功耗为450μW,版图面积为4 800μm^(2)。