Low Voltage Direct Current Supply and Utilization System:Definition,Key Technologies and Development

With rapid increase of distributed solar power generation and direct current(DC)based loads such as data centers,electric vehicles(EVs),and DC household appliances,the development trend of the power system is changed from conventional alternate current(AC)to DC.Traditional AC power systems can scarcely meet the development demand of new DC trends,especially since both the generation side and load side are comprised of DC-based electronic power components.With this background,low voltage direct current supply and utilization system(LVDCSUS)has attracted more and more attention for its great advantages over an AC grid to overcome challenges in operation,reliability,and energy loss in renewable energy connection,DC load power utilization and a number of other aspects.However,the definition of the LVDCSUS is still not clear even though many demonstration projects have been put into planning and operation.In order to provide a clear description of LVDCSUS,first,the characteristics of LVDCSUS are illustrated in this paper to show the advance of the LVDCSUS.Second,the potential application scenarios of LVDCSUS are presented in this paper.Third,application of LVDCSUS technologies and some demonstration projects in China are introduced.Besides the development of the LVDCSUS,key technologies,including but not limited to planning and design,voltage levels,control strategies,and key equipment of LVDCSUS,are discussed in this paper.Finally,future application areas and the research orientations of LVDCSUS are analyzed.

A boosted negative bit-line SRAM with write-assisted cell in 45 nm CMOS technology

A new 11 T SRAM cell with write-assist is proposed to improve operation at low supply voltage. In this technique, a negative bit-line voltage is applied to one of the write bit-lines, while a boosted voltage is applied to the other write bit-line where transmission gate access is used in proposed 11 T cell. Supply voltage to one of the inverters is interrupted to weaken the feedback. Improved write feature is attributed to strengthened write access devices and weakened feedback loop of cell at the same time. Amount of boosting required for write performance improvement is also reduced due to feedback weakening, solving the persistent problem of half-selected cells and reliability reduction of access devices with the other suggested boosted and negative bit-line techniques. The proposed design improves write time by 79%, 63% and slower by 52% with respect to LP 10 T, WRE 8 T and 6 T cells respectively. It is found that write margin for the proposed cell is improved by about 4×, 2.4× and 5.37× compared to WRE8 T, LP10 T and 6 T respectively. The proposed cell with boosted negative bit line（BNBL） provides47%, 31%, and 68.4% improvement in write margin with respect to no write-assist, negative bit line（NBL） and boosted bit line（BBL） write-assist respectively. Also, new sensing circuit with replica bit-line is proposed to give a more precise timing of applying boosted voltages for improved results. All simulations are done on TSMC 45 nm CMOS technology.