Implementation of low-density parity-check codes decoder for CCSDS standard

The complexity/performance balanced decoder for low-density parity-check （LDPC） codes is preferred in practical wireless communication systems. A low complexity LDPC decoder for the Consultative Committee for Space Data Systems （CCSDS） standard is achieved in DSP. An ap- proximate decoding algorithm, normalized rain-sum algorithm, is used in the implementation for its low amounts of computation. To reduce the performance loss caused by the approximation, the pa- rameters of the normalized min-sum algorithm are determined by calculating and finding the mini- mum value of thresholds through density evolution. The minimum value which indicates the best per- formance of the decoding algorithm is corresponding with the optimized parameters. In implementa- tion, the memory cost is saved by decomposing the parity-check matrix into submatrices to store and the computation of passing message in decoding is accelerated by using the intrinsic function of DSP. The performance of the decoder with optimized factors is simulated and compared with the ideal BP decoder. The result shows they have about the same performance.

Low-Complexity Optimization Algorithm for Irregular Low-Density Parity-Check Codes

A low-complexity algorithm is proposed in this paper in order to optimize irregular low-density parity-check(LDPC)codes.The algorithm proposed can calculate the noise threshold by means of a one-dimensional density evolution and search the optimal degree profiles with fast-convergence differential evolution,so that it has a lower complexity and a faster convergence speed.Simulation results show that the irregular LDPC codes optimized by the presented algorithm can also perform better than Turbo codes at moderate block length even with less computation cost.

Low-Density Parity-Check Codes: Research Status and Development Direction

In this paper, we conclude five kinds of methods for construction of the regular low-density parity matrix H and three kinds of methods for the construction of irregular low-density parity-check matrix H. Through the analysis of the code rate and parameters of these eight kinds of structures, we find that the construction of low-density parity-check matrix tends to be more flexible and the parameter variability is enhanced. We propose that the current development cost should be lower with the progress of electronic technology and we need research on more practical Low-Density Parity-Check Codes (LDPC). Combined with the application of the quantum distribution key, we urgently need to explore the research direction of relevant theories and technologies of LDPC codes in other fields of quantum information in the future.

Analysis of LDPC Code in Hybrid Communication Systems

Free-space optical(FSO)communication is of supreme importance for designing next-generation networks.Over the past decades,the radio frequency(RF)spectrum has been the main topic of interest for wireless technology.The RF spectrum is becoming denser and more employed,making its availability tough for additional channels.Optical communication,exploited for messages or indications in historical times,is now becoming famous and useful in combination with error-correcting codes(ECC)to mitigate the effects of fading caused by atmospheric turbulence.A free-space communication system(FSCS)in which the hybrid technology is based on FSO and RF.FSCS is a capable solution to overcome the downsides of current schemes and enhance the overall link reliability and availability.The proposed FSCS with regular low-density parity-check(LDPC)for coding techniques is deliberated and evaluated in terms of signal-to-noise ratio(SNR)in this paper.The extrinsic information transfer(EXIT)methodology is an incredible technique employed to investigate the sum-product decoding algorithm of LDPC codes and optimize the EXIT chart by applying curve fitting.In this research work,we also analyze the behavior of the EXIT chart of regular/irregular LDPC for the FSCS.We also investigate the error performance of LDPC code for the proposed FSCS.

DESIGN OF LOW-DENSITY PARITY CHECK CODES FOR MIMO SYSTEMS WITH DOUBLY-ITERATIVE RECEIVERS

In this paper, the Multiple Input Multiple Output (MIMO) doubly-iterative receiver which consists of the Probabilistic Data Association detector (PDA) and Low-Density Parity-Check Code (LDPC) decoder is developed. The receiver performs two iterative decoding loops. In the outer loop, the soft information is exchanged between the PDA detector and the LDPC decoder. In the inner loop, it is exchanged between variable node and check node decoders inside the LDPC decoder. On the light of the Extrinsic Information Transfer (EXIT) chart technique, an LDPC code degree profile optimization algorithm is developed for the doubly-iterative receiver. Simulation results show the doubly-receiver with optimized irregular LDPC code can have a better performance than the one with the regular one.

Weighted symbol-flipping decoding algorithm for nonbinary LDPC codes with flipping patterns

A novel low-complexity weighted symbol-flipping algorithm with flipping patterns to decode nonbinary low-density parity-check codes is proposed. The proposed decoding procedure updates the hard-decision received symbol vector iteratively in search of a valid codeword in the symbol vector space. Only one symbol is flipped in each iteration, and symbol flipping function, which is employed as the symbol flipping metric, combines the number of failed checks and the reliabilities of the received bits and calculated symbols. A scheme to avoid infinite loops and select one symbol to flip in high order Galois field search is also proposed. The design of flipping pattern＇s order and depth, which is dependent of the computational requirement and error performance, is also proposed and exemplified. Simulation results show that the algorithm achieves an appealing tradeoff between performance and computational requirement over relatively low Galois field for short to medium code length.

Erasure-Correction-Enhanced Iterative Decoding for LDPC-RS Product Codes

Low-density parity-check(LDPC)codes are widely used due to their significant errorcorrection capability and linear decoding complexity.However,it is not sufficient for LDPC codes to satisfy the ultra low bit error rate(BER)requirement of next-generation ultra-high-speed communications due to the error floor phenomenon.According to the residual error characteristics of LDPC codes,we consider using the high rate Reed-Solomon(RS)codes as the outer codes to construct LDPC-RS product codes to eliminate the error floor and propose the hybrid error-erasure-correction decoding algorithm for the outer code to exploit erasure-correction capability effectively.Furthermore,the overall performance of product codes is improved using iteration between outer and inner codes.Simulation results validate that BER of the product code with the proposed hybrid algorithm is lower than that of the product code with no erasure correction.Compared with other product codes using LDPC codes,the proposed LDPC-RS product code with the same code rate has much better performance and smaller rate loss attributed to the maximum distance separable(MDS)property and significant erasure-correction capability of RS codes.

Implementation of encoder and decoder for LDPC codes based on FPGA

This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diagonal parity structure.A normalized min-sum algorithm(NMSA)is employed for decoding.The whole verification of the encoding and decoding algorithm is simulated with Matlab,and the code rates of 5/6 and 2/3 are selected respectively for the initial bit error ratio as 6%and 1.04%.Based on the results of simulation,multi-code rates are compatible with different basis matrices.Then the simulated algorithms of encoder and decoder are migrated and implemented on the field programmable gate array(FPGA).The 183.36 Mbps throughput of encoder and the average 27.85 Mbps decoding throughput with the initial bit error ratio 6%are realized based on FPGA.

Design of good QC-LDPC codes without small girth in the p-plane

A construction method based on the p-plane to design high-girth quasi-cyclic low-density parity-check （QC-LDPC） codes is proposed. Firstly the good points in every line of the p-plane can be ascertained through filtering the bad points, because the designed parity-check matrixes using these points have the short cycles in Tanner graph of codes. Then one of the best points from the residual good points of every line in the p-plane will be found, respectively. The optimal point is also singled out according to the bit error rate （BER） performance of the QC-LDPC codes at last. Explicit necessary and sufficient conditions for the QC-LDPC codes to have no short cycles are presented which are in favor of removing the bad points in the p-plane. Since preventing the short cycles also prevents the small stopping sets, the proposed construction method also leads to QC-LDPC codes with a higher stopping distance.

DESIGN OF QUASI-CYCLIC LDPC CODES BASED ON EUCLIDEAN GEOMETRIES

A new method for constructing Quasi-Cyclic (QC) Low-Density Parity-Check (LDPC) codes based on Euclidean Geometry (EG) is presented. The proposed method results in a class of QC-LDPC codes with girth of at least 6 and the designed codes perform very close to the Shannon limit with iterative decoding. Simulations show that the designed QC-LDPC codes have almost the same performance with the existing EG-LDPC codes.

Ruling out small stopping sets and small girth in Tanner graph of QC-LDPC code

The existing constructions of quasi-cyclic low-density parity-check （QC-LDPC） codes do not consider the problems of small stopping sets and small girth together in the Tanner graph, while their existences will lead to the bit error rate （BER） performance of QC-LDPC codes being much poorer than that of randomly constructed LDPC codes even decoding failure. To solve the problem, some theorems of the specific chosen parity-check matrix of QC-LDPC codes without small stopping sets and small girth are proposed. A novel construction for QC-LDPC codes with long block lengths is presented by multiplying mmin or the multiple of mmin, which is the minimum order of the identity matrix for the chosen parity-check matrix. The simulation results show that the specific chosen parity-check matrix of QC-LDPC codes can effectively avoid specified stopping sets and small girth and exhibit excellent BER performance than random LDPC codes with the same longer codes length.

JOINT ITERATIVE DECODING FOR SIMPLE-ENCODING SYSTEMATIC IRREGULAR-LDPC-BASED CODED COOPERATION IN NON-IDEAL RELAY CHANNEL

In this paper, a new kind of simple-encoding irregular systematic LDPC codes suitable for one-relay coded cooperation is designed, where the proposed joint iterative decoding is effectively performed in the destination which is in accordance with the corresponding joint Tanner graph characterizing two different component LDPC codes used by the source and relay in ideal and non-ideal relay cooperations. The theoretical analysis and simulations show that the coded cooperation scheme obviously outperforms the coded non-cooperation one under the same code rate and decoding complex. The significant performance improvement can be virtually credited to the additional mutual exchange of the extrinsic information resulted by the LDPC code employed by the source and its counterpart used by the relay in both ideal and non-ideal cooperations.

Irregular and regular LDPC codes with high spectrum efficiency modulation in image transmission over fading channel

If the degree distribution is chosen carefully, the irregular low-density parity-check (LDPC) codes can outperform the regular ones. An image transmission system is proposed by combining regular and irregular LDPC codes with 16QAM/64QAM modulation to improve both efficiency and reliability. Simulaton results show that LDPC codes are good coding schemes over fading channel in image communication with lower system complexity. More over, irregular codes can obtain a code gain of about 0.7 dB compared with regular ones when BER is 10 -4. So the irregular LDPC codes are more suitable for image transmission than the regular codes.

Ensemble of High Performance Structured Binary Convolutional LDPC Codes with Moderate Rates

An algebraic construction methodology is proposed to design binary time-invariant convolutional low-density parity-check(LDPC)codes.Assisted by a proposed partial search algorithm,the polynomialform parity-check matrix of the time-invariant convolutional LDPC code is derived by combining some special codewords of an(n,2,n−1)code.The achieved convolutional LDPC codes possess the characteristics of comparatively large girth and given syndrome former memory.The objective of our design is to enable the time-invariant convolutional LDPC codes the advantages of excellent error performance and fast encoding.In particular,the error performance of the proposed convolutional LDPC code with small constraint length is superior to most existing convolutional LDPC codes.

Construction of Regular Rate-Compatible LDPC Convolutional Codes

In this paper, we propose a new method to derive a family of regular rate-compatible low-density parity-check（RC-LDPC） convolutional codes from RC-LDPC block codes. In the RC-LDPC convolutional family, each extended sub-matrix of each extended code is obtained by choosing specified elements from two fixed matrices HE1K and HE1K, which are derived by modifying the extended matrices HE1 and HE2 of a systematic RC-LDPC block code. The proposed method which is based on graph extension simplifies the design, and prevent the defects caused by the puncturing method. It can be used to generate both regular and irregular RC-LDPC convolutional codes. All resulted codes in the family are systematic which simplify the encoder structure and have maximum encoding memories which ensure the property. Simulation results show the family collectively offer a steady improvement in performance with code compatibility over binary-input additive white Gaussian noise channel（BI-AWGNC）.

LLR calculation for LDPC coded SCBT in 60 GHz WPAN

The single-carrier block transmission（SCBT）,a.k.a.,single-carrier frequency-domain equalization（SC-FDE）,is being considered as an option technique for the wireless personal area network（WPAN） operating at 60 GHz.It is found that for residential environment,in non-line-of-sight（NLOS） multi-path channels,the SCBT is much more effective to combat the inter-symbol interference（ISI） compared with orthogonal frequency division multiplexing（OFDM）.Low-density parity-check（LDPC） codes are a class of linear block codes which provide near capacity performance on a large collection of data transmission and storage channels while simultaneously admitting implementable decoders.To facilitate using LDPC codes for SCBT system,a new log-likelihood ratio（LLR） calculation method is proposed based on pilot symbols（PS）.Golay Sequences whose sum autocorrelation has a unique peak and zero sidelobe are used for creating the PS.The position and length of the PS are not fixed in the data blocks.The simulation results show that the proposed method can significantly improve the LDPC decoding performance in SCBT system.This is very promising to support ultra high-data-rate wireless transmission.

Efficient Early Termination Strategy for LDPC Codes in GPS Systems

By exploiting the structural features of L1C messages,a novel Early Termination( ET) strategy is proposed to speed up the decoding of low-density parity-check( LDPC) codes in the GPS system. The proposed strategy is based on the cyclic redundancy check( CRC) of the messages in the subframes 2 and 3. The simulation results show that average number of iterations of the proposed strategy is less than that of the standard ET strategy,with nearly no degradation in decoding performance. Besides,the proposed ET strategy can be efficiently implemented in a sequential or parallel manner. Thus,the proposed ET strategy is attractive for practical purposes.

Performances of Chaos Coded Modulation Schemes Based on Mod-MAP Mapping and High Dimensional LDPC Based Mod-MAP Mapping with Belief Propagation

In this paper, we propose to generalize the coding schemes first proposed by Kozic &al to high spectral efficient modulation schemes. We study at first Chaos Coded Modulation based on the use of small dimensional modulo-MAP encoding process and we give a solution to study the distance spectrum of such coding schemes to accurately predict their performances. However, the obtained performances are quite poor. To improve them, we use then a high dimensional modulo-MAP mapping process similar to the low-density generator-matrix codes (LDGM) introduced by Kozic &al. The main difference with their work is that we use an encoding and decoding process on GF (2m) which enables to obtain better performances while preserving a quite simple decoding algorithm when we use the Extended Min-Sum (EMS) algorithm of Declercq &Fossorier.

Improved iterative convergence method in Q-ary LDPC coded high order PR-CPM

The Q-ary low-density parity-check（LDPC） coded high order partial response continuous phase modulation（PR-CPM） with double iterative loops is investigated. This scheme shows significant improvements in power and bandwidth efficiency, but at the expense of long iterative decoding delay and computational complexity induced by the improper match between the demodulator and the decoder. To address this issue, the convergence behavior of Q-ary LDPC coded CPM is investigated for the Q=2 and Q〉2 cases, and an optimized design method based on the extrinsic information transfer chart is proposed to improve the systematic iterative efficiency. Simulation results demonstrate that the proposed method can achieve a perfect tradeoff between iterative decoding delay and bit error rate performance to satisfy real-time applications.

Construction of Rate-Compatible(RC) Low-Density Parity-Check(LDPC) Convolutional Codes Based on RC-LDPC Block Codes

In this paper,a family of rate-compatible(RC) low-density parity-check(LDPC) convolutional codes can be obtained from RC-LDPC block codes by graph extension method.The resulted RC-LDPC convolutional codes,which are derived by permuting the matrices of the corresponding RC-LDPC block codes,are systematic and have maximum encoding memory.Simulation results show that the proposed RC-LDPC convolutional codes with belief propagation(BP) decoding collectively offer a steady improvement on performance compared with the block counterparts over the binary-input additive white Gaussian noise channels(BI-AWGNCs).