A multiplexer with a low-distortion high-bandwidth analog switch is presented. The gate-to-source voltage of the switch is set by the combined on-voltage of a pMOS and an nMOS,and the difference between its gate-sourc...A multiplexer with a low-distortion high-bandwidth analog switch is presented. The gate-to-source voltage of the switch is set by the combined on-voltage of a pMOS and an nMOS,and the difference between its gate-source voltage and the threshold voltage （VGST） is guaranteed to be constant with input variation. Thus, the body effect is nearly canceled. Implemented in a TSMC 0.18μm CMOS process, results from HSPICE simulation show that the VGST is nearly constant with an input range from 0.3 to 1.7V,and the - 3dB bandwidth is larger than 10GHz;the SFDR （spurious free dynamic range） of the output is 67. lldB with 1GHz input frequency; the turn-on time is 2.98ns,and the turn-off time is 1.35ns, which indicates a break-before-make action of the multiplexer. The proposed structure can be applied to high speed signal transmission.展开更多
A fourth-order low-distortion low-pass sigma-delta （∑△） modulator is presented for micro-machined inertial sensors. The proposed single-loop single-bit feedback modulator is optimized with a feed-forward path to d...A fourth-order low-distortion low-pass sigma-delta （∑△） modulator is presented for micro-machined inertial sensors. The proposed single-loop single-bit feedback modulator is optimized with a feed-forward path to decrease the nonlinearities and power consumption. The IC is implemented in a standard 0.6 μm CMOS technology and operates at a sampling frequency of 3.846 MHz. The chip area is 2.12 mm^2 with 23 pads. The experimental results indicate a signal-to-noise ratio （SNR） of 100 dB and dynamic range （DR） of 103 dB at an oversampling rate （OSR） of 128 with the input signal amplitude of-3.88 dBFS at 9.8 kHz; the power consumption is 15 raW at a 5 V supply.展开更多
Traditional feedforward structures suffer from performance constraints caused by the complex adder before quantizer.This paper presents an improved 4th-order 1 -bit sigma-delta modulator which has a simple adder and d...Traditional feedforward structures suffer from performance constraints caused by the complex adder before quantizer.This paper presents an improved 4th-order 1 -bit sigma-delta modulator which has a simple adder and delayed input feedforward to relax timing constraints and implement low-distortion.The modulator was fabricated in a 0.35μm CMOS process,and it achieved 92.8 dB SNDR and 101 dB DR with a signal bandwidth of 100 kHz dissipating 8.6 mW power from a 3.3-V supply.The performance satisfies the requirements of a GSM system.展开更多
文摘A multiplexer with a low-distortion high-bandwidth analog switch is presented. The gate-to-source voltage of the switch is set by the combined on-voltage of a pMOS and an nMOS,and the difference between its gate-source voltage and the threshold voltage （VGST） is guaranteed to be constant with input variation. Thus, the body effect is nearly canceled. Implemented in a TSMC 0.18μm CMOS process, results from HSPICE simulation show that the VGST is nearly constant with an input range from 0.3 to 1.7V,and the - 3dB bandwidth is larger than 10GHz;the SFDR （spurious free dynamic range） of the output is 67. lldB with 1GHz input frequency; the turn-on time is 2.98ns,and the turn-off time is 1.35ns, which indicates a break-before-make action of the multiplexer. The proposed structure can be applied to high speed signal transmission.
基金supported by the National Natural Science Foundation of China(No.61204121)
文摘A fourth-order low-distortion low-pass sigma-delta （∑△） modulator is presented for micro-machined inertial sensors. The proposed single-loop single-bit feedback modulator is optimized with a feed-forward path to decrease the nonlinearities and power consumption. The IC is implemented in a standard 0.6 μm CMOS technology and operates at a sampling frequency of 3.846 MHz. The chip area is 2.12 mm^2 with 23 pads. The experimental results indicate a signal-to-noise ratio （SNR） of 100 dB and dynamic range （DR） of 103 dB at an oversampling rate （OSR） of 128 with the input signal amplitude of-3.88 dBFS at 9.8 kHz; the power consumption is 15 raW at a 5 V supply.
基金Project supported by the National Science Fund for Distinguished Young Scholars of China(No.60925015)
文摘Traditional feedforward structures suffer from performance constraints caused by the complex adder before quantizer.This paper presents an improved 4th-order 1 -bit sigma-delta modulator which has a simple adder and delayed input feedforward to relax timing constraints and implement low-distortion.The modulator was fabricated in a 0.35μm CMOS process,and it achieved 92.8 dB SNDR and 101 dB DR with a signal bandwidth of 100 kHz dissipating 8.6 mW power from a 3.3-V supply.The performance satisfies the requirements of a GSM system.
