Emerging memristive devices offer enormous advantages for applications such as non-volatile memories and inmemory computing(IMC),but there is a rising interest in using memristive technologies for security application...Emerging memristive devices offer enormous advantages for applications such as non-volatile memories and inmemory computing(IMC),but there is a rising interest in using memristive technologies for security applications in the era of internet of things(IoT).In this review article,for achieving secure hardware systems in IoT,lowpower design techniques based on emerging memristive technology for hardware security primitives/systems are presented.By reviewing the state-of-the-art in three highlighted memristive application areas,i.e.memristive non-volatile memory,memristive reconfigurable logic computing and memristive artificial intelligent computing,their application-level impacts on the novel implementations of secret key generation,crypto functions and machine learning attacks are explored,respectively.For the low-power security applications in IoT,it is essential to understand how to best realize cryptographic circuitry using memristive circuitries,and to assess the implications of memristive crypto implementations on security and to develop novel computing paradigms that will enhance their security.This review article aims to help researchers to explore security solutions,to analyze new possible threats and to develop corresponding protections for the secure hardware systems based on low-cost memristive circuit designs.展开更多
The emphasis of constructing and developing the campus information network is how to design and optimize the network hardware system. This paper mainly studies the network system structure design, the server system st...The emphasis of constructing and developing the campus information network is how to design and optimize the network hardware system. This paper mainly studies the network system structure design, the server system structure design and the network export design, and discusses the network hardware system design and optimization for different scale universities according to different practical demand. The objective is that the network hardware system can meet the demand and have been made full use.展开更多
This paper describes the implementation of a data logger for the real-time in-situ monitoring of hydrothermal systems. A compact mechanical structure ensures the security and reliability of data logger when used under...This paper describes the implementation of a data logger for the real-time in-situ monitoring of hydrothermal systems. A compact mechanical structure ensures the security and reliability of data logger when used under deep sea. The data logger is a battery powered instrument, which can connect chemical sensors (pH electrode, H2S electrode, H2 electrode) and temperature sensors. In order to achieve major energy savings, dynamic power management is implemented in hardware design and software design. The working current of the data logger in idle mode and active mode is 15 μA and 1.44 mA respectively, which greatly extends the working time of battery. The data logger has been successftdly tested in the first Sino-American Cooperative Deep Submergence Project from August 13 to September 3, 2005.展开更多
Depth estimation is an active research area with the developing of stereo vision in recent years. It is one of the key technologies to resolve the large data of stereo vision communication. Now depth estimation still ...Depth estimation is an active research area with the developing of stereo vision in recent years. It is one of the key technologies to resolve the large data of stereo vision communication. Now depth estimation still has some problems, such as occlusion, fuzzy edge, real-time processing, etc. Many algorithms have been proposed base on software, however the performance of the computer configurations limits the software processing speed. The other resolution is hardware design and the great developments of the digital signal processor (DSP), and application specific integrated circuit (ASIC) and field programmable gate array (FPGA) provide the opportunity of flexible applications. In this work, by analyzing the procedures of depth estimation, the proper algorithms which can be used in hardware design to execute real-time depth estimation are proposed. The different methods of calibration, matching and post-processing are analyzed based on the hardware design requirements. At last some tests for the algorithm have been analyzed. The results show that the algorithms proposed for hardware design can provide credited depth map for further view synthesis and are suitable for hardware design.展开更多
A fully hardware-implemented phase calculating system for the feedback control in the lower-hybrid current drive (LHCD) experiments is presented in this paper. By taking advantages of field programmable gate array ...A fully hardware-implemented phase calculating system for the feedback control in the lower-hybrid current drive (LHCD) experiments is presented in this paper. By taking advantages of field programmable gate array (FPGA) chips with embedded digital signal processing (DSP) cores and the Matlab-aided design method, the phase calculating algorithm with a square root operation and parallel process are efficiently implemented in a single FPGA chip to complete the calculation of phase differences fast and accurately in the lower-hybrid wave (LHW) system on EAST.展开更多
This paper deals with a new hardware/software embedded system design methodology based on design pattern approach by development of a new design tool called smartcell. Three main constraints of embedded systems design...This paper deals with a new hardware/software embedded system design methodology based on design pattern approach by development of a new design tool called smartcell. Three main constraints of embedded systems design process are investigated: the complexity, the partitioning between hardware and software aspects and the reusability. Two intermediate models are carried out in order to solve the complexity problem. The partitioning problem deals with the proposed hardware/software partitioning algorithm based on Ant Colony Optimisation. The reusability problem is resolved by synthesis of intellectual property blocks. Specification and integration of an intelligent controller on heterogeneous platform are considered to illustrate the proposed approach.展开更多
In order to eliminate the energy waste caused by the traditional static hardware multithreaded processor used in real-time embedded system working in the low workload situation, the energy efficiency of the hardware m...In order to eliminate the energy waste caused by the traditional static hardware multithreaded processor used in real-time embedded system working in the low workload situation, the energy efficiency of the hardware multithread is discussed and a novel dynamic multithreaded architecture is proposed. The proposed architecture saves the energy wasted by removing idle threads without manipulation on the original architecture, fulfills a seamless switching mechanism which protects active threads and avoids pipeline stall during power mode switching. The report of an implemented dynamic multithreaded processor with 45 nm process from synthesis tool indicates that the area of dynamic multithreaded architecture is only 2.27% higher than the static one in achieving dynamic power dissipation, and consumes 1.3% more power in the same peak performance.展开更多
基金supported by the DFG(German Research Foundation)Priority Program Nano Security,Project MemCrypto(Projektnummer 439827659/funding id DU 1896/2–1,PO 1220/15–1)the funding by the Fraunhofer Internal Programs under Grant No.Attract 600768。
文摘Emerging memristive devices offer enormous advantages for applications such as non-volatile memories and inmemory computing(IMC),but there is a rising interest in using memristive technologies for security applications in the era of internet of things(IoT).In this review article,for achieving secure hardware systems in IoT,lowpower design techniques based on emerging memristive technology for hardware security primitives/systems are presented.By reviewing the state-of-the-art in three highlighted memristive application areas,i.e.memristive non-volatile memory,memristive reconfigurable logic computing and memristive artificial intelligent computing,their application-level impacts on the novel implementations of secret key generation,crypto functions and machine learning attacks are explored,respectively.For the low-power security applications in IoT,it is essential to understand how to best realize cryptographic circuitry using memristive circuitries,and to assess the implications of memristive crypto implementations on security and to develop novel computing paradigms that will enhance their security.This review article aims to help researchers to explore security solutions,to analyze new possible threats and to develop corresponding protections for the secure hardware systems based on low-cost memristive circuit designs.
文摘The emphasis of constructing and developing the campus information network is how to design and optimize the network hardware system. This paper mainly studies the network system structure design, the server system structure design and the network export design, and discusses the network hardware system design and optimization for different scale universities according to different practical demand. The objective is that the network hardware system can meet the demand and have been made full use.
基金supported by the International Cooperative Key Project(Grant No.2004DFA04900)Ministry of Sciences and Technology of PRC,and the National Natural Science Foundation of China (Grant Nos.40637037 and 50675198)
文摘This paper describes the implementation of a data logger for the real-time in-situ monitoring of hydrothermal systems. A compact mechanical structure ensures the security and reliability of data logger when used under deep sea. The data logger is a battery powered instrument, which can connect chemical sensors (pH electrode, H2S electrode, H2 electrode) and temperature sensors. In order to achieve major energy savings, dynamic power management is implemented in hardware design and software design. The working current of the data logger in idle mode and active mode is 15 μA and 1.44 mA respectively, which greatly extends the working time of battery. The data logger has been successftdly tested in the first Sino-American Cooperative Deep Submergence Project from August 13 to September 3, 2005.
基金supported by the National Natural Science Foundation of China(Grant Nos.60832003)the Key Laboratory of Advanced Display and System Applications(Shanghai University),Ministry of Education,China(Grant No.P200801)the Science and Technology Commission of Shanghai Municipality(Grant No.10510500500)
文摘Depth estimation is an active research area with the developing of stereo vision in recent years. It is one of the key technologies to resolve the large data of stereo vision communication. Now depth estimation still has some problems, such as occlusion, fuzzy edge, real-time processing, etc. Many algorithms have been proposed base on software, however the performance of the computer configurations limits the software processing speed. The other resolution is hardware design and the great developments of the digital signal processor (DSP), and application specific integrated circuit (ASIC) and field programmable gate array (FPGA) provide the opportunity of flexible applications. In this work, by analyzing the procedures of depth estimation, the proper algorithms which can be used in hardware design to execute real-time depth estimation are proposed. The different methods of calibration, matching and post-processing are analyzed based on the hardware design requirements. At last some tests for the algorithm have been analyzed. The results show that the algorithms proposed for hardware design can provide credited depth map for further view synthesis and are suitable for hardware design.
文摘A fully hardware-implemented phase calculating system for the feedback control in the lower-hybrid current drive (LHCD) experiments is presented in this paper. By taking advantages of field programmable gate array (FPGA) chips with embedded digital signal processing (DSP) cores and the Matlab-aided design method, the phase calculating algorithm with a square root operation and parallel process are efficiently implemented in a single FPGA chip to complete the calculation of phase differences fast and accurately in the lower-hybrid wave (LHW) system on EAST.
文摘This paper deals with a new hardware/software embedded system design methodology based on design pattern approach by development of a new design tool called smartcell. Three main constraints of embedded systems design process are investigated: the complexity, the partitioning between hardware and software aspects and the reusability. Two intermediate models are carried out in order to solve the complexity problem. The partitioning problem deals with the proposed hardware/software partitioning algorithm based on Ant Colony Optimisation. The reusability problem is resolved by synthesis of intellectual property blocks. Specification and integration of an intelligent controller on heterogeneous platform are considered to illustrate the proposed approach.
基金supported partially by the National High Technical Research and Development Program of China (863 Program) under Grants No. 2011AA040101, No. 2008AA01Z134the National Natural Science Foundation of China under Grants No. 61003251, No. 61172049, No. 61173150+2 种基金the Doctoral Fund of Ministry of Education of China under Grant No. 20100006110015Beijing Municipal Natural Science Foundation under Grant No. Z111100054011078the 2012 Ladder Plan Project of Beijing Key Laboratory of Knowledge Engineering for Materials Science under Grant No. Z121101002812005
文摘In order to eliminate the energy waste caused by the traditional static hardware multithreaded processor used in real-time embedded system working in the low workload situation, the energy efficiency of the hardware multithread is discussed and a novel dynamic multithreaded architecture is proposed. The proposed architecture saves the energy wasted by removing idle threads without manipulation on the original architecture, fulfills a seamless switching mechanism which protects active threads and avoids pipeline stall during power mode switching. The report of an implemented dynamic multithreaded processor with 45 nm process from synthesis tool indicates that the area of dynamic multithreaded architecture is only 2.27% higher than the static one in achieving dynamic power dissipation, and consumes 1.3% more power in the same peak performance.