Temperature-Dependent Effect of Near-Interface Traps on SiC MOS Capacitance

A two-dimensional electrical SiC MOS interface model including interface and near-interface traps is established based on the relevant tunneling and interface Shockley–Read–Hall model. The consistency between simulation results and measured data in the different temperatures shows that this interface model can accurately describe the capture and emission performance for near-interface oxide traps, and can well explain the hysteresis-voltage response with increasing temperature, which is intensified by the interaction between deep oxide traps and shallow oxide traps. This also indicates that the near-interface traps result in an increase of threshold-voltage shift in SiC MOSFET with increasing temperature.

MOS Capacitance-Voltage Characteristics from Electron-Trapping at Dopant Donor Impurity

The capacitance versus DC-voltage formula from electron trapping at dopant impurity centers is de- rived for MOS capacitors by the charge-storage method. Fermi-Dirac distribution and impurity deionization are included in the DC-voltage scale. The low-frequency and high-frequency capacitances, and their differences and derivatives, are computed in the presence of an unlimited source of minority and maj ority carriers. The results show that their difference and their DC-voltage derivatives, are large and readily measurable, hence suitable as a method for characterizing the electronic trapping parameters at dopant impurity centers and for a number of lower power signal processing and device technology monitoring applications.

Design,modelling,and simulation of a floating gate transistor with a novel security feature

This study proposes a new generation of floating gate transistors(FGT)with a novel built-in security feature.The new device has applications in guarding the IC chips against the current reverse engineering techniques,including scanning capacitance microscopy(SCM).The SCM measures the change in the C–V characteristic of the device as a result of placing a minute amount of charge on the floating gate,even in nano-meter scales.The proposed design only adds a simple processing step to the conventional FGT by adding an oppositely doped implanted layer to the substrate.This new structure was first analyzed theoretically and then a two-dimensional model was extracted to represent its C–V characteristic.Furthermore,this model was verified with a simulation.In addition,the C–V characteristics relevant to the SCM measurement of both conventional and the new designed FGT were compared to discuss the effectiveness of the added layer in masking the state of the transistor.The effect of change in doping concentration of the implanted layer on the C–V characteristics was also investigated.Finally,the feasibility of the proposed design was examined by comparing its I–V characteristics with the traditional FGT.

Novel through-silicon vias for enhanced signal integrity in 3D integrated systems

In this paper, a new type of through-silicon via（TSV） for via-first process namely bare TSV, is proposed and analyzed with the aim of mitigating noise coupling problems in 3D integrated systems for advanced technology nodes. The bare TSVs have no insulation layers, and are divided into two types： bare signal TSVs and bare ground TSVs. First, by solving Poisson＇s equation for cylindrical P–N junctions, the bare signal TSVs are shown to be equivalent to conventional signal TSVs according to the simulation results. Then the bare ground TSV is proved to have improved noise-absorption capability when compared with a conventional ground TSV. Also, the proposed bare TSVs offer more advantages to circuits than other noise isolation methods, because the original circuit design,routing and placement can be retained after the application of the bare TSVs.

An efficient method for comprehensive modeling and parasitic extraction of cylindrical through-silicon vias in 3D ICs

To build an accurate electric model for through-silicon vias （TSVs） in 3D integrated circuits （ICs）, a resistance and capacitance （RC） circuit model and related efficient extraction technique are proposed. The circuit model takes both semiconductor and electrostatic effects into account, and is valid for low and medium signal frequencies. The electrostatic capacitances are extracted with a floating random walk based algorithm, and are then combined with the voltage-dependent semiconductor capacitances to form the equivalent circuit. Compared with the method used in Synopsys＇s Sdevice, which completely simulates the electro/semiconductor effects, the proposed method is more efficient and is able to handle the general TSV layout as well. For several TSV structures, the experimental results validate the accuracy of the proposed method for the frequency range from l0 kHz to 1 GHz. The proposed method demonstrated 47× speedup over the Sdevice for the largest 9-TSV case.