Trapping effect in normally-off Al2O3/AlGaN/GaN metal–oxide–semiconductor (MOS) high-electron-mobility transistors (MOS-HEMTs) with post-etch surface treatment was studied in this paper. Diffusion-controlled interfa...Trapping effect in normally-off Al2O3/AlGaN/GaN metal–oxide–semiconductor (MOS) high-electron-mobility transistors (MOS-HEMTs) with post-etch surface treatment was studied in this paper. Diffusion-controlled interface oxidation treatment and wet etch process were adopted to improve the interface quality of MOS-HEMTs. With capacitance–voltage (C–V) measurement, the density of interface and border traps were calculated to be 1.13 × 10^12 cm^−2 and 6.35 × 10^12 cm^−2, effectively reduced by 27% and 14% compared to controlled devices, respectively. Furthermore, the state density distribution of border traps with large activation energy was analyzed using photo-assisted C–V measurement. It is found that irradiation of monochromatic light results in negative shift of C–V curves, which indicates the electron emission process from border traps. The experimental results reveals that the major border traps have an activation energy about 3.29 eV and the change of post-etch surface treatment process has little effect on this major activation energy.展开更多
The performance degradation of gate-recessed metal–oxide–semiconductor high electron mobility transistor(MOSHEMT)is compared with that of conventional high electron mobility transistor(HEMT)under direct current(DC)s...The performance degradation of gate-recessed metal–oxide–semiconductor high electron mobility transistor(MOSHEMT)is compared with that of conventional high electron mobility transistor(HEMT)under direct current(DC)stress,and the degradation mechanism is studied.Under the channel hot electron injection stress,the degradation of gate-recessed MOS-HEMT is more serious than that of conventional HEMT devices due to the combined effect of traps in the barrier layer,and that under the gate dielectric of the device.The threshold voltage of conventional HEMT shows a reduction under the gate electron injection stress,which is caused by the barrier layer traps trapping the injected electrons and releasing them into the channel.However,because of defects under gate dielectrics which can trap the electrons injected from gate and deplete part of the channel,the threshold voltage of gate-recessed MOS-HEMT first increases and then decreases as the conventional HEMT.The saturation phenomenon of threshold voltage degradation under high field stress verifies the existence of threshold voltage reduction effect caused by gate electron injection.展开更多
This paper studies systematically the drain current collapse in AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors （MOS-HEMTs） by applying pulsed stress to the device. Low-temperature layer of Al...This paper studies systematically the drain current collapse in AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors （MOS-HEMTs） by applying pulsed stress to the device. Low-temperature layer of Al2O3 ultrathin film used as both gate dielectric and surface passivation layer was deposited by atomic layer deposition （ALD）. For HEMT, gate turn-on pulses induced large current collapse. However, for MOS-HEMT, no significant current collapse was found in the gate turn-on pulsing mode with different pulse widths, indicating the good passivation effect of ALD Al2O3. A small increase in Id in the drain pulsing mode is due to the relieving of self-heating effect. The comparison of synchronously dynamic pulsed Id - Vds characteristics of HEMT and MOS-HEMT further demonstrated the good passivation effect of ALD Al2O3.展开更多
An improved small-signal parameter extraction technique for short channel enhancement-mode N-polar GaN MOS-HEMT is proposed, which is a combination of a conventional analytical method and optimization techniques. The ...An improved small-signal parameter extraction technique for short channel enhancement-mode N-polar GaN MOS-HEMT is proposed, which is a combination of a conventional analytical method and optimization techniques. The extrinsic parameters such as parasitic capacitance, inductance and resistance are extracted under the pinch-off condition. The intrinsic parameters of the small-signal equivalent circuit（SSEC） have been extracted including gate forward and backward conductance. Different optimization algorithms such as PSO, Quasi Newton and Firefly optimization algorithm is applied to the extracted parameters to minimize the error between modeled and measured S-parameters. The different optimized SSEC models have been validated by comparing the S-parameters and unity current-gain with TCAD simulations and available experimental data from the literature. It is observed that the Firefly algorithm based optimization approach accurately extracts the small-signal model parameters as compared to other optimization algorithm techniques with a minimum error percentage of 1.3%.展开更多
We report on a GaN metal-oxide-semiconductor high electron mobility transistor (MOS-HEMT) using atomic-layer deposited (ALD) Al2O3 as the gate dielectric. Through further decreasing the thickness of the gate oxide to ...We report on a GaN metal-oxide-semiconductor high electron mobility transistor (MOS-HEMT) using atomic-layer deposited (ALD) Al2O3 as the gate dielectric. Through further decreasing the thickness of the gate oxide to 3.5 nm and optimizing the device fabrication process,a device with maximum transconductance of 150 mS/mm was produced. The drain current of this 0.8 μm gate-length MOS-HEMT could reach 800 mA/mm at +3.0 V gate bias. Compared to a conventional AlGaN/GaN HEMT of similar design,better interface property,lower leakage current,and smaller capacitance-voltage (C-V) hysteresis were obtained,and the superiority of this MOS-HEMT device structure with ALD Al2O3 gate dielectric was exhibited.展开更多
We investigate the performance of an 18 nm gate length AIInN/GaN heterostructure underlap double gate MOSFET, using 2D Sentaurus TCAD simulation. The device uses lattice-matched wideband Al0.83In0.17N and narrowband G...We investigate the performance of an 18 nm gate length AIInN/GaN heterostructure underlap double gate MOSFET, using 2D Sentaurus TCAD simulation. The device uses lattice-matched wideband Al0.83In0.17N and narrowband GaN layers, along with high-k Al2O3 as the gate dielectric. The device has an ultrathin body and is designed according to the ITRS specifications. The simulation is done using the hydrodynamic model and interface traps are also considered. Due to the large two-dimensional electron gas （2DEG） density and high velocity, the maximal drain current density achieved is very high. Extensive device simulation of the major device performance metrics such as drain induced barrier lowering （DIBL）, subthreshold slope （SS）, delay, threshold voltage （Vt）, Ion/Ioff ratio and energy delay product have been done for a wide range of gate and underlap lengths. Encouraging results for delay, Ion, DIBL and energy delay product are obtained. The results indicate that there is a need to optimize theIoff and SS values for specific logic design. The proposed AlInN/GaN heterostructure underlap DG MOSFET shows excellent promise as one of the candidates to substitute currently used MOSFETs for future high speed applications.展开更多
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 61704124, 11690042, and 61634005).
文摘Trapping effect in normally-off Al2O3/AlGaN/GaN metal–oxide–semiconductor (MOS) high-electron-mobility transistors (MOS-HEMTs) with post-etch surface treatment was studied in this paper. Diffusion-controlled interface oxidation treatment and wet etch process were adopted to improve the interface quality of MOS-HEMTs. With capacitance–voltage (C–V) measurement, the density of interface and border traps were calculated to be 1.13 × 10^12 cm^−2 and 6.35 × 10^12 cm^−2, effectively reduced by 27% and 14% compared to controlled devices, respectively. Furthermore, the state density distribution of border traps with large activation energy was analyzed using photo-assisted C–V measurement. It is found that irradiation of monochromatic light results in negative shift of C–V curves, which indicates the electron emission process from border traps. The experimental results reveals that the major border traps have an activation energy about 3.29 eV and the change of post-etch surface treatment process has little effect on this major activation energy.
基金the Laboratory Open Fund of Beijing Smart-chip Microelectronics Technology Co.Ltd and the National Natural Science Foundation of China(Grant No.11690042)+1 种基金the Science Challenge Project,China(Grant Nos.TZ2018004 and 12035019)the National Major Scientific Research Instrument Projects,China(Grant No.61727804)。
文摘The performance degradation of gate-recessed metal–oxide–semiconductor high electron mobility transistor(MOSHEMT)is compared with that of conventional high electron mobility transistor(HEMT)under direct current(DC)stress,and the degradation mechanism is studied.Under the channel hot electron injection stress,the degradation of gate-recessed MOS-HEMT is more serious than that of conventional HEMT devices due to the combined effect of traps in the barrier layer,and that under the gate dielectric of the device.The threshold voltage of conventional HEMT shows a reduction under the gate electron injection stress,which is caused by the barrier layer traps trapping the injected electrons and releasing them into the channel.However,because of defects under gate dielectrics which can trap the electrons injected from gate and deplete part of the channel,the threshold voltage of gate-recessed MOS-HEMT first increases and then decreases as the conventional HEMT.The saturation phenomenon of threshold voltage degradation under high field stress verifies the existence of threshold voltage reduction effect caused by gate electron injection.
基金Project supported by NSFC (Grant No 60736033)National 973 Basic Research Project (Grant No 51327020301)
文摘This paper studies systematically the drain current collapse in AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors （MOS-HEMTs） by applying pulsed stress to the device. Low-temperature layer of Al2O3 ultrathin film used as both gate dielectric and surface passivation layer was deposited by atomic layer deposition （ALD）. For HEMT, gate turn-on pulses induced large current collapse. However, for MOS-HEMT, no significant current collapse was found in the gate turn-on pulsing mode with different pulse widths, indicating the good passivation effect of ALD Al2O3. A small increase in Id in the drain pulsing mode is due to the relieving of self-heating effect. The comparison of synchronously dynamic pulsed Id - Vds characteristics of HEMT and MOS-HEMT further demonstrated the good passivation effect of ALD Al2O3.
基金project under the Visvesvaraya PhD Scheme of the Ministry of Electronics&Information Technology,Government of India,being implemented by the Digital IndiaCorporation (formerly Media Lab Asia)TEQIP-Ⅱ funding for facilitating Silvaco TCAD and Keysight's ADS tools for carrying out the research work
文摘An improved small-signal parameter extraction technique for short channel enhancement-mode N-polar GaN MOS-HEMT is proposed, which is a combination of a conventional analytical method and optimization techniques. The extrinsic parameters such as parasitic capacitance, inductance and resistance are extracted under the pinch-off condition. The intrinsic parameters of the small-signal equivalent circuit（SSEC） have been extracted including gate forward and backward conductance. Different optimization algorithms such as PSO, Quasi Newton and Firefly optimization algorithm is applied to the extracted parameters to minimize the error between modeled and measured S-parameters. The different optimized SSEC models have been validated by comparing the S-parameters and unity current-gain with TCAD simulations and available experimental data from the literature. It is observed that the Firefly algorithm based optimization approach accurately extracts the small-signal model parameters as compared to other optimization algorithm techniques with a minimum error percentage of 1.3%.
基金Supported by the National Natural Science Foundation of China (Grant No. 60736033)the National Basic Research Program of China ("973") (Grant No. 51327020301)
文摘We report on a GaN metal-oxide-semiconductor high electron mobility transistor (MOS-HEMT) using atomic-layer deposited (ALD) Al2O3 as the gate dielectric. Through further decreasing the thickness of the gate oxide to 3.5 nm and optimizing the device fabrication process,a device with maximum transconductance of 150 mS/mm was produced. The drain current of this 0.8 μm gate-length MOS-HEMT could reach 800 mA/mm at +3.0 V gate bias. Compared to a conventional AlGaN/GaN HEMT of similar design,better interface property,lower leakage current,and smaller capacitance-voltage (C-V) hysteresis were obtained,and the superiority of this MOS-HEMT device structure with ALD Al2O3 gate dielectric was exhibited.
文摘We investigate the performance of an 18 nm gate length AIInN/GaN heterostructure underlap double gate MOSFET, using 2D Sentaurus TCAD simulation. The device uses lattice-matched wideband Al0.83In0.17N and narrowband GaN layers, along with high-k Al2O3 as the gate dielectric. The device has an ultrathin body and is designed according to the ITRS specifications. The simulation is done using the hydrodynamic model and interface traps are also considered. Due to the large two-dimensional electron gas （2DEG） density and high velocity, the maximal drain current density achieved is very high. Extensive device simulation of the major device performance metrics such as drain induced barrier lowering （DIBL）, subthreshold slope （SS）, delay, threshold voltage （Vt）, Ion/Ioff ratio and energy delay product have been done for a wide range of gate and underlap lengths. Encouraging results for delay, Ion, DIBL and energy delay product are obtained. The results indicate that there is a need to optimize theIoff and SS values for specific logic design. The proposed AlInN/GaN heterostructure underlap DG MOSFET shows excellent promise as one of the candidates to substitute currently used MOSFETs for future high speed applications.
