Various biaxial compressive strained GaSb p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) are experimentally and theoretically investigated, The biaxial compressive strained GaSb MOSFETs show ...Various biaxial compressive strained GaSb p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) are experimentally and theoretically investigated, The biaxial compressive strained GaSb MOSFETs show a high peak mobility of 638 cm2/V.s, which is 3.86 times of the extracted mobility of the fabricated GaSb MOSFETs without strain. Meanwhile, first principles calculations show that the hole effective mass of GaSb depends on the biaxial compressive strain. The biaxiai compressive strain brings a remarkable enhancement of the hole mobility caused by a significant reduction in the hole effective mass due to the modulation of the valence bands.展开更多
The influence of total dose irradiation on hot-carrier reliability of 65 nm n-type metal-oxide-semiconductor field- effect transistors (nMOSFETs) is investigated. Experimental results show that hot-carrier degradati...The influence of total dose irradiation on hot-carrier reliability of 65 nm n-type metal-oxide-semiconductor field- effect transistors (nMOSFETs) is investigated. Experimental results show that hot-carrier degradations on ir- radiated narrow channel nMOSFETs are greater than those without irradiation. The reason is attributed to radiation-induced charge trapping in shallow trench isolation (STI). The electric field in the pinch-off region of the nMOSFET is enhanced by radiation-induced charge trapping in STI, resulting in a more severe hot-carrier effect.展开更多
A power metal-oxide-semiconductor field-effect transistor(MOSFET) with dielectric trench is investigated to enhance the reversed blocking capability. The dielectric trench with a low permittivity to reduce the electri...A power metal-oxide-semiconductor field-effect transistor(MOSFET) with dielectric trench is investigated to enhance the reversed blocking capability. The dielectric trench with a low permittivity to reduce the electric field at reversed blocking state has been studied. To analyze the electric field, the drift region is segmented into four regions, where the conformal mapping method based on Schwarz–Christoffel transformation has been applied. According to the analysis, the improvement in the electric field for using the low permittivity trench is mainly due to the two electric field peaks generated in the drift region around this dielectric trench. The analytical results of the electric field and the potential models are in good agreement with the simulation results.展开更多
In this paper, TiN/A1Ox gated A1GaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOS- HFETs) were fabricated for gate-first process evaluation. By employing a low temperature ohmic process...In this paper, TiN/A1Ox gated A1GaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOS- HFETs) were fabricated for gate-first process evaluation. By employing a low temperature ohmic process, ohmic contact can be obtained by annealing at 600 ℃ with the contact resistance approximately 1.6 Ω.mm. The ohmic annealing process also acts as a post-deposition annealing on the oxide film, resulting in good device performance. Those results demonstrated that the TiN/A1Ox gated MOS-HFETs with low temperature ohmic process can be applied for self-aligned gate AIGaN/GaN MOS-HFETs.展开更多
Ultra-thin-body (UTB) In0.53Ga0.47As-on-insulator (In0.53Ga0.47As-OI) structures with thicknesses of 8 and 15nm are realized by transferring epitaxially grown In0.53Ga0.47As layers to silicon substrates with 15-nm...Ultra-thin-body (UTB) In0.53Ga0.47As-on-insulator (In0.53Ga0.47As-OI) structures with thicknesses of 8 and 15nm are realized by transferring epitaxially grown In0.53Ga0.47As layers to silicon substrates with 15-nmthick A12 03 as a buried oxide by using the direct wafer bonding method. Back gate n-channel metal-oxidesemiconductor field-effect transistors (nMOSFETs) are fabricated by using these In0.53Ga0.47As-OI structures with excellent electrical characteristics. Positive bias temperature instability (PBTI) and hot carrier injection (HCI) characterizations are performed for the In0.53Ga0.47As-OI nMOSFETs. It is confirmed that the In0.53Ga0.47 As-OI nMOSFETs with a thinner body thickness suffer from more severe degradations under both PBTI and HCr stresses. Moreover, the different evolutions of the threshold voltage and the saturation current of the UTB In0.53Ga0.47As-OI nMOSFETs may be due to the slow border traps.展开更多
The fabrication and characterization of 1700 V 7 A 4H-SiC vertical double-implanted metal-oxide-semiconductor field-effect transistors (VDMOSFETs) are reported. The drift layer is 17μm in thickness with 5 × 10...The fabrication and characterization of 1700 V 7 A 4H-SiC vertical double-implanted metal-oxide-semiconductor field-effect transistors (VDMOSFETs) are reported. The drift layer is 17μm in thickness with 5 × 10^15 cm^-3 n-type doping, and the channel length is 1μm. The MOSFETs show a peak mobility of 17cm2/V.s and a typical threshold voltage of 3 V. The active area of 0.028cm2 delivers a forward drain current of 7A at Vcs = 22 V and VDS= 15 V. The specific on-resistance (Ron,sv) is 18mΩ.cm2 at VGS= 22 V and the blocking voltage is 1975 V (IDS 〈 lOOnA) at VGS = 0 V.展开更多
Negative Bias Temperature Instability (NBTI) has become one of the most serious reliability problems of metaloxide-semiconductor field-effect transistors (MOSFETs). The degradation mechanism and model of NBTI are ...Negative Bias Temperature Instability (NBTI) has become one of the most serious reliability problems of metaloxide-semiconductor field-effect transistors (MOSFETs). The degradation mechanism and model of NBTI are studied in this paper. From the experimental results, the exponential value 0.25-0.5 which represents the relation of NBTI degradation and stress time is obtained. Based on the experimental results and existing model, the reaction-diffusion model with H^+ related species generated is deduced, and the exponent 0.5 is obtained. The results suggest that there should be H^+ generated in the NBTI degradation. With the real time method, the degradation with an exponent 0.5 appears clearly in drain current shift during the first seconds of stress and then verifies that H^+ generated during NBTI stress.展开更多
GaSb p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with an atomic layer deposited Al2O3 gate dielectric and a self-aligned Si-implanted source/drain are experimentally demonstrated. Temperat...GaSb p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with an atomic layer deposited Al2O3 gate dielectric and a self-aligned Si-implanted source/drain are experimentally demonstrated. Temperature dependent electrical characteristics are investigated. Different electrical behaviors are observed in two temperature regions, and the un- derlying mechanisms are discussed. It is found that the reverse-bias pn junction leakage of the drain/substrate is the main component of the off-state drain leakage current, which is generation-current dominated in the low temperature regions and is diffusion-current dominated in the high temperature regions. Methods to further reduce the off-state drain leakage current are given.展开更多
Models of threshold voltage and subthreshold swing, including the fringing-capacitance effects between the gate electrode and the surface of the source/drain region, are proposed. The validity of the proposed models i...Models of threshold voltage and subthreshold swing, including the fringing-capacitance effects between the gate electrode and the surface of the source/drain region, are proposed. The validity of the proposed models is confirmed by the good agreement between the simulated results and the experimental data. Based on the models, some factors impacting the threshold voltage and subthreshold swing of a GeOI metal-oxide-semiconductor field-effect transistor(MOSFET) are discussed in detail and it is found that there is an optimum thickness of gate oxide for definite dielectric constant of gate oxide to obtain the minimum subthreshold swing. As a result, it is shown that the fringing-capacitance effect of a shortchannel GeOI MOSFET cannot be ignored in calculating the threshold voltage and subthreshold swing.展开更多
Ge complementary tunneling field-effect transistors(TFETs) are fabricated with the NiGe metal source/drain(S/D) structure. The dopant segregation method is employed to form the NiGe/Ge tunneling junctions of suffi...Ge complementary tunneling field-effect transistors(TFETs) are fabricated with the NiGe metal source/drain(S/D) structure. The dopant segregation method is employed to form the NiGe/Ge tunneling junctions of sufficiently high Schottky barrier heights. As a result, the Ge p-and n-TFETs exhibit decent electrical properties of large ON-state current and steep sub-threshold slope(S factor). Especially, I_d of 0.2 μA/μm is revealed at V_g-V_(th) = V_d = ±0.5 V for Ge pTFETs,with the S factor of 28 mV/dec at 7 K.展开更多
Experiments and simulation studies on 283 MeV I ion induced single event effects of silicon carbide(SiC) metal–oxide–semiconductor field-effect transistors(MOSFETs) were carried out. When the cumulative irradiation ...Experiments and simulation studies on 283 MeV I ion induced single event effects of silicon carbide(SiC) metal–oxide–semiconductor field-effect transistors(MOSFETs) were carried out. When the cumulative irradiation fluence of the SiC MOSFET reached 5×10^(6)ion·cm^(-2), the drain–gate channel current increased under 200 V drain voltage, the drain–gate channel current and the drain–source channel current increased under 350 V drain voltage. The device occurred single event burnout under 800 V drain voltage, resulting in a complete loss of breakdown voltage. Combined with emission microscope, scanning electron microscope and focused ion beam analysis, the device with increased drain–gate channel current and drain–source channel current was found to have drain–gate channel current leakage point and local source metal melt, and the device with single event burnout was found to have local melting of its gate, source, epitaxial layer and substrate. Combining with Monte Carlo simulation and TCAD electrothermal simulation, it was found that the initial area of single event burnout might occur at the source–gate corner or the substrate–epitaxial interface, electric field and current density both affected the lattice temperature peak. The excessive lattice temperature during the irradiation process appeared at the local source contact, which led to the drain–source channel damage. And the excessive electric field appeared in the gate oxide layer, resulting in drain–gate channel damage.展开更多
In this paper, the normally-off N-channel lateral 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSF- FETs) have been fabricated and characterized. A sandwich- (nitridation-oxidation-nitridation) type...In this paper, the normally-off N-channel lateral 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSF- FETs) have been fabricated and characterized. A sandwich- (nitridation-oxidation-nitridation) type process was used to grow the gate dielectric film to obtain high channel mobility. The interface properties of 4H-SiC/SiO2 were examined by the measurement of HF l-V, G-V, and C-V over a range of frequencies. The ideal C-V curve with little hysteresis and the frequency dispersion were observed. As a result, the interface state density near the conduction band edge of 4H-SiC was reduced to 2 x 1011 eV-l.cm-2, the breakdown field of the grown oxides was about 9.8 MV/cm, the median peak field- effect mobility is about 32.5 cm2.V-1 .s-1, and the maximum peak field-effect mobility of 38 cm2-V-1 .s-1 was achieved in fabricated lateral 4H-SiC MOSFFETs.展开更多
We present an experimental analysis of Schottky-barrier metal-oxide-semiconductor field effect transistors (SB- MOSFETs) fabricated on ultrathin body silicon-on-insulator substrates with a steep junction by the dopa...We present an experimental analysis of Schottky-barrier metal-oxide-semiconductor field effect transistors (SB- MOSFETs) fabricated on ultrathin body silicon-on-insulator substrates with a steep junction by the dopant implantation into the silicide process. The subthreshold swing of such SB-MOSFETs reaches 69mV/dec. Em- phasis is placed on the capacitance-voltage analysis of p-type SB-MOSFETs. According to the measurements of gate-to-source capacitance Cgs with respect to Vgs at various Vds, we find that a maximum occurs at the accumulation regime due to the most imbalanced charge distribution along the channel. At each Cgs peak, the difference between Vgs and Vds is equal to the Schottky barrier height (SBH) for NiSi2 on highly doped silicon, which indicates that the critical condition of channel pinching off is related with SBH for source/drain on chan- nel. The SBH for NiSi2 on highly doped silicon can affect the pinch-off voltage and the saturation current of SB-MOSFETs.展开更多
Radiation effects of silicon carbide metal–oxide–semiconductor field-effect transistors(SiC MOSFETs)induced by 20 MeV proton under drain bias(V_(D)=800 V,V_(G)=0 V),gate bias(V_(D)=0 V,V_(G)=10 V),turn-on bias(V_(D)...Radiation effects of silicon carbide metal–oxide–semiconductor field-effect transistors(SiC MOSFETs)induced by 20 MeV proton under drain bias(V_(D)=800 V,V_(G)=0 V),gate bias(V_(D)=0 V,V_(G)=10 V),turn-on bias(V_(D)=0.5 V,V_(G)=4 V)and static bias(V_(D)=0 V,V_(G)=0 V)are investigated.The drain current of SiC MOSFET under turn-on bias increases linearly with the increase of proton fluence during the proton irradiation.When the cumulative proton fluence reaches 2×10^(11)p·cm^(-2),the threshold voltage of SiC MOSFETs with four bias conditions shifts to the left,and the degradation of electrical characteristics of SiC MOSFETs with gate bias is the most serious.In the deep level transient spectrum test,it is found that the defect energy level of SiC MOSFET is mainly the ON2(E_(c)-1.1 eV)defect center,and the defect concentration and defect capture cross section of SiC MOSFET with proton radiation under gate bias increase most.By comparing the degradation of SiC MOSFET under proton cumulative irradiation,equivalent 1 MeV neutron irradiation and gamma irradiation,and combining with the defect change of SiC MOSFET under gamma irradiation and the non-ionizing energy loss induced by equivalent 1 MeV neutron in SiC MOSFET,the degradation of SiC MOSFET induced by proton is mainly caused by ionizing radiation damage.The results of TCAD analysis show that the ionizing radiation damage of SiC MOSFET is affected by the intensity and direction of the electric field in the oxide layer and epitaxial layer.展开更多
A silicon (Si)/silicon carbide (4H-SiC) heterojunction double-trench metal-oxide-semiconductor field effect transistor (MOSFET) (HDT-MOS) with the gate-controlled tunneling effect is proposed for the first time based ...A silicon (Si)/silicon carbide (4H-SiC) heterojunction double-trench metal-oxide-semiconductor field effect transistor (MOSFET) (HDT-MOS) with the gate-controlled tunneling effect is proposed for the first time based on simulations. In this structure, the channel regions are made of Si to take advantage of its high channel mobility and carrier density. The voltage-withstanding region is made of 4H-SiC so that HDT-MOS has a high breakdown voltage (BV) similar to pure 4H-SiC double-trench MOSFETs (DT-MOSs). The gate-controlled tunneling effect indicates that the gate voltage (V_(G)) has a remarkable influence on the tunneling current of the heterojunction. The accumulation layer formed with positive VG can reduce the width of the Si/SiC heterointerface barrier, similar to the heavily doped region in an Ohmic contact. This narrower barrier is easier for electrons to tunnel through, resulting in a lower heterointerface resistance. Thus, with similar BV (approximately 1770 V), the specific on-state resistance (R_(ON-SP)) of HDT-MOS is reduced by 0.77 mΩ·cm^(2) compared with that of DT-MOS. The gate-to-drain charge (Q_(GD)) and switching loss of HDT-MOS are 52.14% and 22.59% lower than those of DT-MOS, respectively, due to the lower gate platform voltage (V_(GP)) and the corresponding smaller variation (ΔV_(GP)). The figure of merit (Q_(GD)×R_(ON-SP)) of HDT-MOS decreases by 61.25%. Moreover, the heterointerface charges can reduce RON-SP of HDT-MOS due to trap-assisted tunneling while the heterointerface traps show the opposite effect. Therefore, the HDT-MOS structure can significantly reduce the working loss of SiC MOSFET, leading to a lower temperature rise when the devices are applied in the system.展开更多
Based on the analysis of vertical electric potential distribution across the dual-channel strained p-type Si/strained Si1-xGex/relaxd Si1-yGey(s-Si/s-SiGe/Si1-yGey) metal-oxide-semiconductor field-effect transistor ...Based on the analysis of vertical electric potential distribution across the dual-channel strained p-type Si/strained Si1-xGex/relaxd Si1-yGey(s-Si/s-SiGe/Si1-yGey) metal-oxide-semiconductor field-effect transistor (PMOSFET), analytical expressions of the threshold voltages for buried channel and surface channel are presented. And the maximum allowed thickness of s-Si is given, which can ensure that the strong inversion appears earlier in the buried channel (compressive strained SiGe) than in the surface channel (tensile strained Si), because the hole mobility in the buried channel is higher than that in the surface channel. Thus they offer a good accuracy as compared with the results of device simulator ISE. With this model, the variations of threshold voltage and maximum allowed thickness of s-Si with design parameters can be predicted, such as Ge fraction, layer thickness, and doping concentration. This model can serve as a useful tool for p-channel s-Si/s-SiGe/Si1-yGey metal-oxide-semiconductor field-effect transistor (MOSFET) designs.展开更多
Growing a silicon(Si) layer on top of stacked Si-germanium(Ge) compressive layer can introduce a tensile strain on the former, resulting in superior device characteristics. Such a structure can be used for high perfor...Growing a silicon(Si) layer on top of stacked Si-germanium(Ge) compressive layer can introduce a tensile strain on the former, resulting in superior device characteristics. Such a structure can be used for high performance complementary metal-oxide-semiconductor(CMOS) circuits. Down scaling metal-oxide-semiconductor field-effect transistors(MOSFETs) into the deep submicron/nanometer regime forces the source(S) and drain(D) series resistance to become comparable with the channel resistance and thus it cannot be neglected. Owing to the persisting technological importance of strained Si devices, in this work, we propose a multi-iterative technique for evaluating the performance of strained-Si/strained-Si_(1-y)Ge_y/relaxed-Si_(1-x)Ge_x MOSFETs and its related circuits in the presence of S/D series resistance, leading to the development of a simulator that can faithfully plot the performance of the device and related digital circuits. The impact of strain on device/circuit performance is also investigated with emphasis on metal gate and high-k dielectric materials.展开更多
In this paper the influences of the metal-gate and high-k/SiO 2 /Si stacked structure on the metal-oxide-semiconductor field-effect transistor(MOSFET) are investigated.The flat-band voltage is revised by considering...In this paper the influences of the metal-gate and high-k/SiO 2 /Si stacked structure on the metal-oxide-semiconductor field-effect transistor(MOSFET) are investigated.The flat-band voltage is revised by considering the influences of stacked structure and metal-semiconductor work function fluctuation.The two-dimensional Poisson's equation of potential distribution is presented.A threshold voltage analytical model for metal-gate/high-k/SiO 2 /Si stacked MOSFETs is developed by solving these Poisson's equations using the boundary conditions.The model is verified by a two-dimensional device simulator,which provides the basic design guidance for metal-gate/high-k/SiO 2 /Si stacked MOSFETs.展开更多
基金Project supported by the National Basic Research Program of China(Grant No.2011CBA00602)the National Science and Technology Major Project of the Ministry of Science and Technology of China(Grant No.2011ZX02708-002)
文摘Various biaxial compressive strained GaSb p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) are experimentally and theoretically investigated, The biaxial compressive strained GaSb MOSFETs show a high peak mobility of 638 cm2/V.s, which is 3.86 times of the extracted mobility of the fabricated GaSb MOSFETs without strain. Meanwhile, first principles calculations show that the hole effective mass of GaSb depends on the biaxial compressive strain. The biaxiai compressive strain brings a remarkable enhancement of the hole mobility caused by a significant reduction in the hole effective mass due to the modulation of the valence bands.
基金Supported by the National Natural Science Foundation of China under Grant Nos 11475255,U1532261 and 11505282
文摘The influence of total dose irradiation on hot-carrier reliability of 65 nm n-type metal-oxide-semiconductor field- effect transistors (nMOSFETs) is investigated. Experimental results show that hot-carrier degradations on ir- radiated narrow channel nMOSFETs are greater than those without irradiation. The reason is attributed to radiation-induced charge trapping in shallow trench isolation (STI). The electric field in the pinch-off region of the nMOSFET is enhanced by radiation-induced charge trapping in STI, resulting in a more severe hot-carrier effect.
基金Project supported by the National Natural Science Foundation of China(Grant No.61404110)the National Higher-education Institution General Research and Development Project,China(Grant No.2682014CX097)
文摘A power metal-oxide-semiconductor field-effect transistor(MOSFET) with dielectric trench is investigated to enhance the reversed blocking capability. The dielectric trench with a low permittivity to reduce the electric field at reversed blocking state has been studied. To analyze the electric field, the drift region is segmented into four regions, where the conformal mapping method based on Schwarz–Christoffel transformation has been applied. According to the analysis, the improvement in the electric field for using the low permittivity trench is mainly due to the two electric field peaks generated in the drift region around this dielectric trench. The analytical results of the electric field and the potential models are in good agreement with the simulation results.
基金Project supported by the International Science and Technology Collaboration Program of China(Grant No.2012DFG52260)
文摘In this paper, TiN/A1Ox gated A1GaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOS- HFETs) were fabricated for gate-first process evaluation. By employing a low temperature ohmic process, ohmic contact can be obtained by annealing at 600 ℃ with the contact resistance approximately 1.6 Ω.mm. The ohmic annealing process also acts as a post-deposition annealing on the oxide film, resulting in good device performance. Those results demonstrated that the TiN/A1Ox gated MOS-HFETs with low temperature ohmic process can be applied for self-aligned gate AIGaN/GaN MOS-HFETs.
基金Supported by the National Program on Key Basic Research Project of China under Grant No 2011CBA00607the National Natural Science Foundation of China under Grant Nos 61106089 and 61376097the Zhejiang Provincial Natural Science Foundation of China under Grant No LR14F040001
文摘Ultra-thin-body (UTB) In0.53Ga0.47As-on-insulator (In0.53Ga0.47As-OI) structures with thicknesses of 8 and 15nm are realized by transferring epitaxially grown In0.53Ga0.47As layers to silicon substrates with 15-nmthick A12 03 as a buried oxide by using the direct wafer bonding method. Back gate n-channel metal-oxidesemiconductor field-effect transistors (nMOSFETs) are fabricated by using these In0.53Ga0.47As-OI structures with excellent electrical characteristics. Positive bias temperature instability (PBTI) and hot carrier injection (HCI) characterizations are performed for the In0.53Ga0.47As-OI nMOSFETs. It is confirmed that the In0.53Ga0.47 As-OI nMOSFETs with a thinner body thickness suffer from more severe degradations under both PBTI and HCr stresses. Moreover, the different evolutions of the threshold voltage and the saturation current of the UTB In0.53Ga0.47As-OI nMOSFETs may be due to the slow border traps.
基金Supported by the National Science and Technology Major Project of the Ministry of Science and Technology of China under Grant No 2013ZX02305
文摘The fabrication and characterization of 1700 V 7 A 4H-SiC vertical double-implanted metal-oxide-semiconductor field-effect transistors (VDMOSFETs) are reported. The drift layer is 17μm in thickness with 5 × 10^15 cm^-3 n-type doping, and the channel length is 1μm. The MOSFETs show a peak mobility of 17cm2/V.s and a typical threshold voltage of 3 V. The active area of 0.028cm2 delivers a forward drain current of 7A at Vcs = 22 V and VDS= 15 V. The specific on-resistance (Ron,sv) is 18mΩ.cm2 at VGS= 22 V and the blocking voltage is 1975 V (IDS 〈 lOOnA) at VGS = 0 V.
基金supported by the Fundamental Research Funds in Xidian Universities (Grant No.JY10000904009)the National Key Technology Research and Development Program of the Ministry of Science and Technology of China (Grant No.2007BAK25B03)
文摘Negative Bias Temperature Instability (NBTI) has become one of the most serious reliability problems of metaloxide-semiconductor field-effect transistors (MOSFETs). The degradation mechanism and model of NBTI are studied in this paper. From the experimental results, the exponential value 0.25-0.5 which represents the relation of NBTI degradation and stress time is obtained. Based on the experimental results and existing model, the reaction-diffusion model with H^+ related species generated is deduced, and the exponent 0.5 is obtained. The results suggest that there should be H^+ generated in the NBTI degradation. With the real time method, the degradation with an exponent 0.5 appears clearly in drain current shift during the first seconds of stress and then verifies that H^+ generated during NBTI stress.
基金Project supported by the National Basic Research Program of China(Grant No.2011CBA00602)the National Science and Technology Major Project of the Ministry of Science and Technology of China(Grant No.2011ZX02708-002)
文摘GaSb p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with an atomic layer deposited Al2O3 gate dielectric and a self-aligned Si-implanted source/drain are experimentally demonstrated. Temperature dependent electrical characteristics are investigated. Different electrical behaviors are observed in two temperature regions, and the un- derlying mechanisms are discussed. It is found that the reverse-bias pn junction leakage of the drain/substrate is the main component of the off-state drain leakage current, which is generation-current dominated in the low temperature regions and is diffusion-current dominated in the high temperature regions. Methods to further reduce the off-state drain leakage current are given.
基金supported by the National Natural Science Foundation of China(Grant No.61274112)
文摘Models of threshold voltage and subthreshold swing, including the fringing-capacitance effects between the gate electrode and the surface of the source/drain region, are proposed. The validity of the proposed models is confirmed by the good agreement between the simulated results and the experimental data. Based on the models, some factors impacting the threshold voltage and subthreshold swing of a GeOI metal-oxide-semiconductor field-effect transistor(MOSFET) are discussed in detail and it is found that there is an optimum thickness of gate oxide for definite dielectric constant of gate oxide to obtain the minimum subthreshold swing. As a result, it is shown that the fringing-capacitance effect of a shortchannel GeOI MOSFET cannot be ignored in calculating the threshold voltage and subthreshold swing.
基金Supported by the National Natural Science Foundation of China under Grant No 61504120the Zhejiang Provincial Natural Science Foundation of China under Grant No LR18F040001the Fundamental Research Funds for the Central Universities
文摘Ge complementary tunneling field-effect transistors(TFETs) are fabricated with the NiGe metal source/drain(S/D) structure. The dopant segregation method is employed to form the NiGe/Ge tunneling junctions of sufficiently high Schottky barrier heights. As a result, the Ge p-and n-TFETs exhibit decent electrical properties of large ON-state current and steep sub-threshold slope(S factor). Especially, I_d of 0.2 μA/μm is revealed at V_g-V_(th) = V_d = ±0.5 V for Ge pTFETs,with the S factor of 28 mV/dec at 7 K.
基金supported by the National Natural Science Foundation of China (Grant No. 12075065)。
文摘Experiments and simulation studies on 283 MeV I ion induced single event effects of silicon carbide(SiC) metal–oxide–semiconductor field-effect transistors(MOSFETs) were carried out. When the cumulative irradiation fluence of the SiC MOSFET reached 5×10^(6)ion·cm^(-2), the drain–gate channel current increased under 200 V drain voltage, the drain–gate channel current and the drain–source channel current increased under 350 V drain voltage. The device occurred single event burnout under 800 V drain voltage, resulting in a complete loss of breakdown voltage. Combined with emission microscope, scanning electron microscope and focused ion beam analysis, the device with increased drain–gate channel current and drain–source channel current was found to have drain–gate channel current leakage point and local source metal melt, and the device with single event burnout was found to have local melting of its gate, source, epitaxial layer and substrate. Combining with Monte Carlo simulation and TCAD electrothermal simulation, it was found that the initial area of single event burnout might occur at the source–gate corner or the substrate–epitaxial interface, electric field and current density both affected the lattice temperature peak. The excessive lattice temperature during the irradiation process appeared at the local source contact, which led to the drain–source channel damage. And the excessive electric field appeared in the gate oxide layer, resulting in drain–gate channel damage.
基金Projcet supported by the National Natural Science Foundation of China(Grant Nos.61404098,61176070,and 61274079)the Doctoral Fund of Ministry Education of China(Grant Nos.20110203110010 and 20130203120017)+1 种基金the National Key Basic Research Program of China(Grant No.2015CB75960the Key Specific Projects of Ministry of Education of China(Grant No.625010101)
文摘In this paper, the normally-off N-channel lateral 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSF- FETs) have been fabricated and characterized. A sandwich- (nitridation-oxidation-nitridation) type process was used to grow the gate dielectric film to obtain high channel mobility. The interface properties of 4H-SiC/SiO2 were examined by the measurement of HF l-V, G-V, and C-V over a range of frequencies. The ideal C-V curve with little hysteresis and the frequency dispersion were observed. As a result, the interface state density near the conduction band edge of 4H-SiC was reduced to 2 x 1011 eV-l.cm-2, the breakdown field of the grown oxides was about 9.8 MV/cm, the median peak field- effect mobility is about 32.5 cm2.V-1 .s-1, and the maximum peak field-effect mobility of 38 cm2-V-1 .s-1 was achieved in fabricated lateral 4H-SiC MOSFFETs.
基金Supported by the National Natural Science Foundation of China under Grant No 61674161the Open Project of State Key Laboratory of Functional Materials for Informatics
文摘We present an experimental analysis of Schottky-barrier metal-oxide-semiconductor field effect transistors (SB- MOSFETs) fabricated on ultrathin body silicon-on-insulator substrates with a steep junction by the dopant implantation into the silicide process. The subthreshold swing of such SB-MOSFETs reaches 69mV/dec. Em- phasis is placed on the capacitance-voltage analysis of p-type SB-MOSFETs. According to the measurements of gate-to-source capacitance Cgs with respect to Vgs at various Vds, we find that a maximum occurs at the accumulation regime due to the most imbalanced charge distribution along the channel. At each Cgs peak, the difference between Vgs and Vds is equal to the Schottky barrier height (SBH) for NiSi2 on highly doped silicon, which indicates that the critical condition of channel pinching off is related with SBH for source/drain on chan- nel. The SBH for NiSi2 on highly doped silicon can affect the pinch-off voltage and the saturation current of SB-MOSFETs.
基金Project supported by the National Natural Science Foundation of China(Grant No.12075065)。
文摘Radiation effects of silicon carbide metal–oxide–semiconductor field-effect transistors(SiC MOSFETs)induced by 20 MeV proton under drain bias(V_(D)=800 V,V_(G)=0 V),gate bias(V_(D)=0 V,V_(G)=10 V),turn-on bias(V_(D)=0.5 V,V_(G)=4 V)and static bias(V_(D)=0 V,V_(G)=0 V)are investigated.The drain current of SiC MOSFET under turn-on bias increases linearly with the increase of proton fluence during the proton irradiation.When the cumulative proton fluence reaches 2×10^(11)p·cm^(-2),the threshold voltage of SiC MOSFETs with four bias conditions shifts to the left,and the degradation of electrical characteristics of SiC MOSFETs with gate bias is the most serious.In the deep level transient spectrum test,it is found that the defect energy level of SiC MOSFET is mainly the ON2(E_(c)-1.1 eV)defect center,and the defect concentration and defect capture cross section of SiC MOSFET with proton radiation under gate bias increase most.By comparing the degradation of SiC MOSFET under proton cumulative irradiation,equivalent 1 MeV neutron irradiation and gamma irradiation,and combining with the defect change of SiC MOSFET under gamma irradiation and the non-ionizing energy loss induced by equivalent 1 MeV neutron in SiC MOSFET,the degradation of SiC MOSFET induced by proton is mainly caused by ionizing radiation damage.The results of TCAD analysis show that the ionizing radiation damage of SiC MOSFET is affected by the intensity and direction of the electric field in the oxide layer and epitaxial layer.
基金the Major Science and Technology Program of Anhui Province under Grant No.2020b05050007.
文摘A silicon (Si)/silicon carbide (4H-SiC) heterojunction double-trench metal-oxide-semiconductor field effect transistor (MOSFET) (HDT-MOS) with the gate-controlled tunneling effect is proposed for the first time based on simulations. In this structure, the channel regions are made of Si to take advantage of its high channel mobility and carrier density. The voltage-withstanding region is made of 4H-SiC so that HDT-MOS has a high breakdown voltage (BV) similar to pure 4H-SiC double-trench MOSFETs (DT-MOSs). The gate-controlled tunneling effect indicates that the gate voltage (V_(G)) has a remarkable influence on the tunneling current of the heterojunction. The accumulation layer formed with positive VG can reduce the width of the Si/SiC heterointerface barrier, similar to the heavily doped region in an Ohmic contact. This narrower barrier is easier for electrons to tunnel through, resulting in a lower heterointerface resistance. Thus, with similar BV (approximately 1770 V), the specific on-state resistance (R_(ON-SP)) of HDT-MOS is reduced by 0.77 mΩ·cm^(2) compared with that of DT-MOS. The gate-to-drain charge (Q_(GD)) and switching loss of HDT-MOS are 52.14% and 22.59% lower than those of DT-MOS, respectively, due to the lower gate platform voltage (V_(GP)) and the corresponding smaller variation (ΔV_(GP)). The figure of merit (Q_(GD)×R_(ON-SP)) of HDT-MOS decreases by 61.25%. Moreover, the heterointerface charges can reduce RON-SP of HDT-MOS due to trap-assisted tunneling while the heterointerface traps show the opposite effect. Therefore, the HDT-MOS structure can significantly reduce the working loss of SiC MOSFET, leading to a lower temperature rise when the devices are applied in the system.
基金Project supported by the National Defence Pre-research Foundation of China (Grant Nos. 51308040203,9140A08060407DZ0103,and 6139801)
文摘Based on the analysis of vertical electric potential distribution across the dual-channel strained p-type Si/strained Si1-xGex/relaxd Si1-yGey(s-Si/s-SiGe/Si1-yGey) metal-oxide-semiconductor field-effect transistor (PMOSFET), analytical expressions of the threshold voltages for buried channel and surface channel are presented. And the maximum allowed thickness of s-Si is given, which can ensure that the strong inversion appears earlier in the buried channel (compressive strained SiGe) than in the surface channel (tensile strained Si), because the hole mobility in the buried channel is higher than that in the surface channel. Thus they offer a good accuracy as compared with the results of device simulator ISE. With this model, the variations of threshold voltage and maximum allowed thickness of s-Si with design parameters can be predicted, such as Ge fraction, layer thickness, and doping concentration. This model can serve as a useful tool for p-channel s-Si/s-SiGe/Si1-yGey metal-oxide-semiconductor field-effect transistor (MOSFET) designs.
文摘Growing a silicon(Si) layer on top of stacked Si-germanium(Ge) compressive layer can introduce a tensile strain on the former, resulting in superior device characteristics. Such a structure can be used for high performance complementary metal-oxide-semiconductor(CMOS) circuits. Down scaling metal-oxide-semiconductor field-effect transistors(MOSFETs) into the deep submicron/nanometer regime forces the source(S) and drain(D) series resistance to become comparable with the channel resistance and thus it cannot be neglected. Owing to the persisting technological importance of strained Si devices, in this work, we propose a multi-iterative technique for evaluating the performance of strained-Si/strained-Si_(1-y)Ge_y/relaxed-Si_(1-x)Ge_x MOSFETs and its related circuits in the presence of S/D series resistance, leading to the development of a simulator that can faithfully plot the performance of the device and related digital circuits. The impact of strain on device/circuit performance is also investigated with emphasis on metal gate and high-k dielectric materials.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 60936005 and 61076097)the Cultivation Fund of the Key Scientific and Technical Innovation Project,Ministry of Education of China (Grant No. 708083)the Fundamental Research Funds for the Central Universities (Grant No. 20110203110012)
文摘In this paper the influences of the metal-gate and high-k/SiO 2 /Si stacked structure on the metal-oxide-semiconductor field-effect transistor(MOSFET) are investigated.The flat-band voltage is revised by considering the influences of stacked structure and metal-semiconductor work function fluctuation.The two-dimensional Poisson's equation of potential distribution is presented.A threshold voltage analytical model for metal-gate/high-k/SiO 2 /Si stacked MOSFETs is developed by solving these Poisson's equations using the boundary conditions.The model is verified by a two-dimensional device simulator,which provides the basic design guidance for metal-gate/high-k/SiO 2 /Si stacked MOSFETs.