随着以太网技术和集成电路技术的发展,以太网物理层(Physical Layer,PHY)芯片的速率和性能都得到了极大提升,电路复杂度更是几何级增长,以至于常规的自动测试设备(Automatic Test Equipment,ATE)测试很难充分验证其功能,所以亟需开展相...随着以太网技术和集成电路技术的发展,以太网物理层(Physical Layer,PHY)芯片的速率和性能都得到了极大提升,电路复杂度更是几何级增长,以至于常规的自动测试设备(Automatic Test Equipment,ATE)测试很难充分验证其功能,所以亟需开展相应测试方法研究。提出了一种高效的基于ZYNQ MPSOC的以太网PHY芯片功能测试方法。该方法以ZYNQ MPSOC为核心,设计了一种直达应用层面的系统级测试装置,从而减少了与物理层直接交互的行为,有效降低了测试装置及程序开发难度。经试验验证,提出的基于ZYNQ MPSOC的以太网PHY芯片功能测试方法能够用于以太网PHY芯片测试。展开更多
Thanks to the emerging 3D integration technology, The multiprocessor system on chips （MPSoCs） can now integrate more IP cores on chip with improved energy efficiency. However, several severe challenges also rise up ...Thanks to the emerging 3D integration technology, The multiprocessor system on chips （MPSoCs） can now integrate more IP cores on chip with improved energy efficiency. However, several severe challenges also rise up for 3D ICs due to the die-stacking architecture. Among them, power supply noise becomes a big concern. In the paper, we investigate power supply noise （PSN） interactions among different cores and tiers and show that PSN variations largely depend on task assignments. On the other hand, high integration density incurs a severe thermal issue on 3D ICs. In the paper, we propose a novel task scheduling framework considering both the PSN and the thermal issue. It mainly consists of three parts. First, we extract current stimuli of running tasks by analyzing their power traces derived from architecture level simulations. Second, we develop an efficient power delivery network （PDN） solver to evaluate PSN magnitudes efficiently. Third, we propose a heuristic algorithm to solve the formulated task scheduling problem. Compared with the state-of-the-art task assignment algorithm, the proposed method can reduce PSN by 12% on a 2 × 2 × 2 3D MPSoCs and by 14% on a 3 × 3 × 3 3D MPSoCs. The end-to-end task execution time also improves as much as 5.5% and 7.8% respectively due to the suppressed PSN.展开更多
随着集成技术的快速发展,使得单个芯片上集成IP核数目越来越多。然而,晶体管密度和处理器工作频率的不断提升,使得功耗密度持续增加,导致芯片热量的不断上升。因此,MPSoCs面临不可避免的散热问题。提出了一种基于处理器核区域均温(Regio...随着集成技术的快速发展,使得单个芯片上集成IP核数目越来越多。然而,晶体管密度和处理器工作频率的不断提升,使得功耗密度持续增加,导致芯片热量的不断上升。因此,MPSoCs面临不可避免的散热问题。提出了一种基于处理器核区域均温(Regional Mean Temperature,RMT)的初始任务分配策略,该方法充分考虑到处理器核区域温度。通过向量距离计算处理器核温度梯度,使用遗传算法进行初始任务分配。实验结果表明,该策略相比于随机任务分配策略,峰值温度降低率、热点降低率和温度梯度降低率最高分别达到4.69%、42.31%和77.49%。展开更多
基金This work was supported by the National Natural Science Foundation of China under Grant Nos. 61401008 and 61602022, and the State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, under Grant No. CARCH201602.
文摘Thanks to the emerging 3D integration technology, The multiprocessor system on chips （MPSoCs） can now integrate more IP cores on chip with improved energy efficiency. However, several severe challenges also rise up for 3D ICs due to the die-stacking architecture. Among them, power supply noise becomes a big concern. In the paper, we investigate power supply noise （PSN） interactions among different cores and tiers and show that PSN variations largely depend on task assignments. On the other hand, high integration density incurs a severe thermal issue on 3D ICs. In the paper, we propose a novel task scheduling framework considering both the PSN and the thermal issue. It mainly consists of three parts. First, we extract current stimuli of running tasks by analyzing their power traces derived from architecture level simulations. Second, we develop an efficient power delivery network （PDN） solver to evaluate PSN magnitudes efficiently. Third, we propose a heuristic algorithm to solve the formulated task scheduling problem. Compared with the state-of-the-art task assignment algorithm, the proposed method can reduce PSN by 12% on a 2 × 2 × 2 3D MPSoCs and by 14% on a 3 × 3 × 3 3D MPSoCs. The end-to-end task execution time also improves as much as 5.5% and 7.8% respectively due to the suppressed PSN.
文摘随着集成技术的快速发展,使得单个芯片上集成IP核数目越来越多。然而,晶体管密度和处理器工作频率的不断提升,使得功耗密度持续增加,导致芯片热量的不断上升。因此,MPSoCs面临不可避免的散热问题。提出了一种基于处理器核区域均温(Regional Mean Temperature,RMT)的初始任务分配策略,该方法充分考虑到处理器核区域温度。通过向量距离计算处理器核温度梯度,使用遗传算法进行初始任务分配。实验结果表明,该策略相比于随机任务分配策略,峰值温度降低率、热点降低率和温度梯度降低率最高分别达到4.69%、42.31%和77.49%。
