针对第六代移动通信(The 6th Generation Mobile Communication,6G)中一体化需求感知精度较低的问题,提出一种基于最小频移键控(Minimum Shift Keying,MSK)与线性调频(Linear Frequency Modulation,LFM)的光载太赫兹通感一体化信号的产...针对第六代移动通信(The 6th Generation Mobile Communication,6G)中一体化需求感知精度较低的问题,提出一种基于最小频移键控(Minimum Shift Keying,MSK)与线性调频(Linear Frequency Modulation,LFM)的光载太赫兹通感一体化信号的产生与传输方案。利用MSK-LFM信号在太赫兹频段同时实现通信和感知测距,在通信接收端使用数字信号处理降低无线通信误码率,在感知接收端利用去啁啾技术进行测距。仿真结果表明,MSK-LFM信号在235 GHz太赫兹频段能够实现8 Gbit·s^(-1)的无线通信速率,在距离感知精度上达到了3.75 cm的距离分辨率,且通信误码率低于软判决阈值。当直流偏置为0.8时,8 GHz带宽的MSK-LFM信号通感性能达到平衡,该方案与M相移键控与线性调频(Phase Shift Keying,Linear Frequency Modulation,MPSK-LFM)信号方案相比,在相同通信速率下具有更高的感知测距精度。展开更多
A CMOS fully-differential 2.4GHz ∑-△ frequency synthesizer for Gaussian minimum shift keying （GMSK）modulation is presented. A pre-compensation fractional-N phase-locked loop（PLL）is adopted in the modulator.The t...A CMOS fully-differential 2.4GHz ∑-△ frequency synthesizer for Gaussian minimum shift keying （GMSK）modulation is presented. A pre-compensation fractional-N phase-locked loop（PLL）is adopted in the modulator.The transfer function of the type- Ⅱ third-order phase-locked loop is deduced,and the important parameters that affect the loop transfer function are pointed out. Methods to calibrate the important loop parameters arc introduced. A differential tuned LC-VCO and a fully-differential charge pump are adopted in the PLL design. The designed circuits are simulated in a 0.18gm 1P6M CMOS process. The power consumption of the PLL is only about llmW with the low power consideration in building blocks design, and the data rate of the modulator can reach 2Mb/s.展开更多
文摘A CMOS fully-differential 2.4GHz ∑-△ frequency synthesizer for Gaussian minimum shift keying （GMSK）modulation is presented. A pre-compensation fractional-N phase-locked loop（PLL）is adopted in the modulator.The transfer function of the type- Ⅱ third-order phase-locked loop is deduced,and the important parameters that affect the loop transfer function are pointed out. Methods to calibrate the important loop parameters arc introduced. A differential tuned LC-VCO and a fully-differential charge pump are adopted in the PLL design. The designed circuits are simulated in a 0.18gm 1P6M CMOS process. The power consumption of the PLL is only about llmW with the low power consideration in building blocks design, and the data rate of the modulator can reach 2Mb/s.
