Proposal for sequential Stern-Gerlach experiment with programmable quantum processors

The historical significance of the Stern–Gerlach(SG)experiment lies in its provision of the initial evidence for space quantization.Over time,its sequential form has evolved into an elegant paradigm that effectively illustrates the fundamental principles of quantum theory.To date,the practical implementation of the sequential SG experiment has not been fully achieved.In this study,we demonstrate the capability of programmable quantum processors to simulate the sequential SG experiment.The specific parametric shallow quantum circuits,which are suitable for the limitations of current noisy quantum hardware,are given to replicate the functionality of SG devices with the ability to perform measurements in different directions.Surprisingly,it has been demonstrated that Wigner’s SG interferometer can be readily implemented in our sequential quantum circuit.With the utilization of the identical circuits,it is also feasible to implement Wheeler’s delayed-choice experiment.We propose the utilization of cross-shaped programmable quantum processors to showcase sequential experiments,and the simulation results demonstrate a strong alignment with theoretical predictions.With the rapid advancement of cloud-based quantum computing,such as BAQIS Quafu,it is our belief that the proposed solution is well-suited for deployment on the cloud,allowing for public accessibility.Our findings not only expand the potential applications of quantum computers,but also contribute to a deeper comprehension of the fundamental principles underlying quantum theory.

Efficient cache replacement framework based on access hotness for spacecraft processors

A notable portion of cachelines in real-world workloads exhibits inner non-uniform access behaviors.However,modern cache management rarely considers this fine-grained feature,which impacts the effective cache capacity of contemporary high-performance spacecraft processors.To harness these non-uniform access behaviors,an efficient cache replacement framework featuring an auxiliary cache specifically designed to retain evicted hot data was proposed.This framework reconstructs the cache replacement policy,facilitating data migration between the main cache and the auxiliary cache.Unlike traditional cacheline-granularity policies,the approach excels at identifying and evicting infrequently used data,thereby optimizing cache utilization.The evaluation shows impressive performance improvement,especially on workloads with irregular access patterns.Benefiting from fine granularity,the proposal achieves superior storage efficiency compared with commonly used cache management schemes,providing a potential optimization opportunity for modern resource-constrained processors,such as spacecraft processors.Furthermore,the framework complements existing modern cache replacement policies and can be seamlessly integrated with minimal modifications,enhancing their overall efficacy.

A Scalable Interconnection Scheme in Many-Core Systems

Recent architectures of multi-core systems may have a relatively large number of cores that typically ranges from tens to hundreds;therefore called many-core systems.Such systems require an efficient interconnection network that tries to address two major problems.First,the overhead of power and area cost and its effect on scalability.Second,high access latency is caused by multiple cores’simultaneous accesses of the same shared module.This paper presents an interconnection scheme called N-conjugate Shuffle Clusters(NCSC)based on multi-core multicluster architecture to reduce the overhead of the just mentioned problems.NCSC eliminated the need for router devices and their complexity and hence reduced the power and area costs.It also resigned and distributed the shared caches across the interconnection network to increase the ability for simultaneous access and hence reduce the access latency.For intra-cluster communication,Multi-port Content Addressable Memory(MPCAM)is used.The experimental results using four clusters and four cores each indicated that the average access latency for a write process is 1.14785±0.04532 ns which is nearly equal to the latency of a write operation in MPCAM.Moreover,it was demonstrated that the average read latency within a cluster is 1.26226±0.090591 ns and around 1.92738±0.139588 ns for read access between cores from different clusters.

Typhoon Case Comparison Analysis Between Heterogeneous Many-Core and Homogenous Multicore Supercomputing Platforms

In this paper,a typical experiment is carried out based on a high-resolution air-sea coupled model,namely,the coupled ocean-atmosphere-wave-sediment transport(COAWST)model,on both heterogeneous many-core(SW)and homogenous multicore(Intel)supercomputing platforms.We construct a hindcast of Typhoon Lekima on both the SW and Intel platforms,compare the simulation results between these two platforms and compare the key elements of the atmospheric and ocean modules to reanalysis data.The comparative experiment in this typhoon case indicates that the domestic many-core computing platform and general cluster yield almost no differences in the simulated typhoon path and intensity,and the differences in surface pressure(PSFC)in the WRF model and sea surface temperature(SST)in the short-range forecast are very small,whereas a major difference can be identified at high latitudes after the first 10 days.Further heat budget analysis verifies that the differences in SST after 10 days are mainly caused by shortwave radiation variations,as influenced by subsequently generated typhoons in the system.These typhoons generated in the hindcast after the first 10 days attain obviously different trajectories between the two platforms.

Energy Efficient Hyperparameter Tuned Deep Neural Network to Improve Accuracy of Near-Threshold Processor

When it comes to decreasing margins and increasing energy effi-ciency in near-threshold and sub-threshold processors,timing error resilience may be viewed as a potentially lucrative alternative to examine.On the other hand,the currently employed approaches have certain restrictions,including high levels of design complexity,severe time constraints on error consolidation and propagation,and uncontaminated architectural registers(ARs).The design of near-threshold circuits,often known as NT circuits,is becoming the approach of choice for the construction of energy-efficient digital circuits.As a result of the exponentially decreased driving current,there was a reduction in performance,which was one of the downsides.Numerous studies have advised the use of NT techniques to chip multiprocessors as a means to preserve outstanding energy efficiency while minimising performance loss.Over the past several years,there has been a clear growth in interest in the development of artificial intelligence hardware with low energy consumption(AI).This has resulted in both large corporations and start-ups producing items that compete on the basis of varying degrees of performance and energy use.This technology’s ultimate goal was to provide levels of efficiency and performance that could not be achieved with graphics processing units or general-purpose CPUs.To achieve this objective,the technology was created to integrate several processing units into a single chip.To accomplish this purpose,the hardware was designed with a number of unique properties.In this study,an Energy Effi-cient Hyperparameter Tuned Deep Neural Network(EEHPT-DNN)model for Variation-Tolerant Near-Threshold Processor was developed.In order to improve the energy efficiency of artificial intelligence(AI),the EEHPT-DNN model employs several AI techniques.The notion focuses mostly on the repercussions of embedded technologies positioned at the network’s edge.The presented model employs a deep stacked sparse autoencoder(DSSAE)model with the objective of creating a variation-tolerant NT processor.The time-consuming method of modifying hyperparameters through trial and error is substituted with the marine predators optimization algorithm(MPO).This method is utilised to modify the hyperparameters associated with the DSSAE model.To validate that the proposed EEHPT-DNN model has a higher degree of functionality,a full simulation study is conducted,and the results are analysed from a variety of perspectives.This was completed so that the enhanced performance could be evaluated and analysed.According to the results of the study that compared numerous DL models,the EEHPT-DNN model performed significantly better than the other models.

用于单片机实验教学的红外激光气体检测仪

为了实现科研反哺教学、促进教学与科研的深度融合,研制了一种基于嵌入式多核处理器和数字信号处理器的实验教学用红外激光气体检测仪。该检测仪包括光学系统和电学系统,其中电学系统包含光谱信息感知模块和嵌入式控制模块。利用研制的检测仪开展了氨制冷冷库现场的泄漏氨气浓度的检测应用。结果表明,与传统气体检测仪相比,该检测仪实现了检测仪的网络化与智能化,而且性能满足实验教学要求。

基于MOMA的可重入混合流水车间调度问题研究

针对可重入制造系统多具有多品种、大规模、混流生产等特点,构建带批处理机的可重入混合流水车间调度问题(reentrant hybrid flow shop scheduling problem with batch processors,BPRHFSP)模型,提出一种改进的多目标蜉蝣算法(multi-objective mayfly algorithm,MOMA)进行求解。提出了单件加工阶段和批处理阶段的解码规则;设计了基于Logistic混沌映射的反向学习初始化策略、改进的蜉蝣交配和变异策略,提高了算法初始解的质量和局部搜索能力;根据编码规则设计了基于变邻域下降搜索的蜉蝣运动策略,优化了种群方向。通过对不同规模大量测试算例的仿真实验,验证了MOMA相比传统算法求解BP-RHFSP更具有效性和优越性。所提出的模型能够反映生产的基础特征,达到减少最大完工时间、机器负载和碳排放的目的。

Controller Design for Induction and Brushless Motors Using Matlab with Digital Signal Processor (DSP)

The automation process is a very important pillar for Industry 4.0.One of the first steps is the control of motors to improve production efficiency and generate energy savings.In mass production industries,techniques such as digital signal processing(DSP)systems are implemented to control motors.These systems are efficient but very expensive for certain applications.From this arises the need for a controller capable of handling AC and DC motors that improves efficiency and maintains low energy consumption.This project presents the design of an adaptive control system for brushless AC induction and DC motors,which is functional to any type of plant in the industry.The design was possible by implementing Matlab software and tools such as digital signal processor(DSP)and Simulink.Through an extensive investigation of the state of the art,three models needed to represent the control system have been specified.The first model for the AC motor,the second for the DC motor and the third for the DSP control;this is done in this way so that the probability of failure is lower.Subsequently,these models have been programmed in Simulink,integrating the three main models into one.In this way,the design of a controller for use in AC induction motors,specifically squirrel cage and brushless DC motors,has been achieved.The final model represents a response time of 0.25 seconds,which is optimal for this type of application,where response times of 2e-3 to 3 seconds are expected.

基于Amdahl定律的异构多核密码处理器能效模型研究

边缘计算安全的资源受限特征及各种新型密码技术的应用,对多核密码处理器的高能效、异构性提出需求,但当前尚缺乏相关的异构多核能效模型研究.本文基于扩展Amdahl定律,引入密码串并特征、异构多核结构、数据准备时间、动态电压频率调节等因素,将核划分空闲、活跃状态,建立异构多核密码处理器的能效模型.MATLAB仿真结果表明,数据准备时间占比小于10%时,对能效的负面影响大幅下降;固定电压,频率缩放会影响能效值大小;处理器核空闲/活跃能耗比例越小,能效值越大.架构上,固定异构核,同构核数量与密码任务最大并行度相等时能效值最大,最佳异构核数可由模型变化参数仿真得到;多任务调度执行上,流水与并发执行有利于能效值的进一步提升.多核密码处理器芯片板级测试结果表明,仿真结果与实测数据相关系数接近1,芯片实测的数据准备时间、电压频率缩放等因素的影响与仿真分析基本一致,验证了所提能效模型的有效性.该文重点从影响能效变化趋势因素上,为多核密码处理器异构、高能效设计提供一定的理论分析基础与建议.

基于ARM的电阻炉炉温控制系统设计

在科学技术突飞猛进发展的背景下,现代工业生产中的电压、电流、开关量等都是重要的被控参数,在冶金制造业中,温度是器件生产过程中非常重要的物理参数,需要对各种加热炉的温度进行严格控制,对其温度变化进行实时监测,确保炉内温度满足制造器件的需求。电阻炉在金属热处理中具有较为广泛的应用,是进行金属锻压加热、烧结的重要工业设备。电阻炉温度控制多采用自动化控制系统,实现智能化管理,保证炉温的均匀度以及零件温度的均匀性,提高生产的可靠性和稳定性。从电阻炉温度控制的难点入手分析,结合电阻炉温度控制系统的设计原则,提出一种基于ARM处理器的电阻炉炉温控制系统设计方案,能够提高电阻炉温度控制的精度,保证工业生产的稳定性。

电极间隙对脉冲电场处理器杀菌效果的影响

脉冲电场是新型非热杀菌技术,杀菌效率高、有效保留液体食品的营养成分,具有广阔的应用前景。电极间隙作为脉冲电场杀菌处理器的关键指标,决定处理器的电场分布和杀菌效果。为了获得最佳间隙参数,提升杀菌效果,为此设计了共场型脉冲电场处理器,电极间距分别为3、5和7 mm,针对固定电导率(等效鲜榨柚子汁电导率)的2种典型细菌(金黄色葡萄球菌和大肠杆菌)菌悬液,研究了脉冲电场的杀菌效果。研究发现,3 mm电极间距所能施加最大电压为18 kV,5、7 mm的可达30 kV;处理时间为120 s时,3种间隙的杀菌效率均可达99.99%。因此,综合考虑电源性能、设备能耗和处理能力,首选3 mm电极间距为处理器的应用参数。评估外施电压幅值对杀菌效果的影响,发现细菌存活量的下降趋势可根据其下降速率分为“慢-快-慢”3个阶段。结合菌悬液上清液蛋白质含量的上升趋势,充分说明了电穿孔应为脉冲电场的主要杀菌机制。

基于昇腾AI处理器的轻量化MNG-YOLO模型研究

随着目标检测神经网络算法精度不断提升,算法的参数量以及计算量都有着较高的增长,导致模型实际应用部署困难,因此对神经网络模型进行轻量化,减少模型的参数量和计算量对模型部署在边缘设备上是至关重要的。昇腾AI处理器是华为推出的一款专用于神经网络加速的芯片,为充分发挥昇腾AI处理器的优势并解决算法模型较为庞大的问题,基于此平台提出一种轻量化目标检测模型MNG-YOLO,对YOLO模型采用轻量级主干网络和Ghost卷积以减小模型大小,添加NAM注意力模块和Mish激活函数提升模型准确率。实验结果表明,MNG-YOLO模型相比于原始模型参数量以及计算量均减少约75%,参数量从7 015 519个减少至1 739 799个,计算量从15.8 GFLOPs减少至3.5 GFLOPs,模型精确度也由95.9%提升至97.5%。同时,在昇腾AI处理器上的推理速度达到205 FPS,远超实时性检测的速度要求。

MVSim:面向VLIW多核向量处理器的快速、可扩展和精确的体系结构模拟器

设计了一个面向VLIW多核向量处理器的快速、可扩展、精确的体系结构模拟器MVSim。设计了可扩展的VLIW多核向量处理器模型、多级存储体系结构模型和多核性能模型;实现了指令集架构的节拍精准模拟,Cache、DMA和多核同步部件的高效功能模拟,采用多线程技术实现了多核处理器的高效和可扩展模拟。实验结果表明,MVSim能够准确模拟多核处理器的目标程序执行,模拟结果完全正确,具有良好的可扩展性。MVSim的平均模拟速度分别是RTL模拟和CCS的227倍和5倍,平均性能误差约为2.9%。

长向量处理器高效RNN推理方法

模型深度的不断增加和处理序列长度的不一致对循环神经网络在不同处理器上的性能优化提出巨大挑战。针对自主研制的长向量处理器FT-M7032,实现了一个高效的循环神经网络加速引擎。该引擎采用行优先矩阵向量乘算法和数据感知的多核并行方式,提高矩阵向量乘的计算效率;采用两级内核融合优化方法降低临时数据传输的开销;采用手写汇编优化多种算子,进一步挖掘长向量处理器的性能潜力。实验表明,长向量处理器循环神经网络推理引擎可获得较高性能,相较于多核ARM CPU以及Intel Golden CPU,类循环神经网络模型长短记忆网络可获得最高62.68倍和3.12倍的性能加速。

基于RISC-V的超标量处理器的ROB压缩方法

RISC-V指令集具有灵活可扩展的优势,向量扩展是其扩展指令集之一。在实现向量扩展时需要将向量指令拆分成多条微指令,如果每条微指令都占用一项重排序缓存(ROB),会存在一定的信息冗余,并且会减少CPU中并行执行的指令(in-flight指令)数量,影响处理器性能。基于指令与微指令在ROB中的存储解耦方法,使用一个新的队列(RAB)存储每条微指令的目的寄存器的重命名映射关系等信息,每项ROB只存储其对应指令拆分的微指令的公共信息,ROB与RAB分别控制指令与微指令的提交与回滚,减少了存储信息冗余,缓解了由向量指令拆分的微指令过多导致的in-flight指令数量减少问题。在上述方法的基础上,同时实现了标量指令的ROB压缩,在ROB项数不变的情况下,增加了in-flight指令的最大数量。最终的仿真结果表明,此方法有效提高了处理器性能。

小型推进器转轮五轴数控加工

以小型推进器转轮的五轴数控加工为研究对象,根据曲面造型理论进行转轮的三维数字化建模,并进行数控加工工艺规划和编程,基于双转台型五轴数控机床重点提出了具有RTCP功能的后置处理器开发关键技术,通过国内自主生产的双转台五轴联动加工中心完成小型推进器转轮的加工。经检测,加工的推进器转轮样件满足质量要求,验证了刀具路径和后置处理器的正确性和可靠性。充分发挥了五轴数控机床的加工潜能,同时也为其他类似复杂曲面类零件五轴数控加工提供了可借鉴的方案。

一种基于异构处理器的可动态布署设计与实现

针对卫星支持的多种生活服务需求实时切换、资源灵活智能调用需求,基于无线广域信号服务异构处理器,设计了一种即时高效、动态切换部署处理器功能的方案。通过对大资源FPGA及多片8核DSP多种功能定制结合动态部署设计,实现实时动态可重构处理器系统功能,将5种FPGA应用结合2种DSP应用程序动态组合,配合各功能任务架构需求重建控制、数据链路,完成多任务智能切换。

基于ARM处理器的温室大棚智能监控系统设计

为了实现温室大棚的智能监测与控制,设计基于ARM处理器的温室大棚智能监控系统。系统分为三个部分:数据采集及设备控制终端、智能网关终端、Android手机客户端,数据采集及设备控制终端以ARM微处理为核心,通过传感器、算法、Wi-Fi等技术,实现温室大棚数据采集、数据处理、数据传输及执行设备的智能控制,智能网关终端实现多个温室大棚数据从内网发送至公网,Android手机客户端实现数据的接收与发送。经测试验证,系统能够实现温室大棚的智能监控。

基于嵌入式的温室大棚远程视频监控系统设计与实现

针对农业大棚环境复杂等问题,开发基于嵌入式的温室大棚远程视频监控系统。系统以Hi3519AV100处理器为核心,利用红外摄像头、V4L2技术、视频压缩技术采集温室大棚视频信息,通过5G无线网络、socket网络编程将视频信息发送至数据库服务器及Android手机端,经测试验证系统满足温室大棚远程实时监控要求。

嵌入式处理器自定义指令迭代识别方法仿真

嵌入式系统中的硬件资源是有限的,并且自定义指令和原始指令之间可能存在冲突,导致指令代码识别精准度降低、运行功耗较高。为此,提出嵌入式处理器自定义指令迭代低功耗识别方法。对嵌入式处理器的指令代码展开可视化处理,将指令图像输入卷积神经网络中,检测指令代码中存在的恶意代码,采用开源编译器将代码转变为控制数据流图,枚举并选择子图,通过代码转换完成嵌入式处理器自定义指令识别。仿真结果表明,所提方法的恶意代码检测精度高、代码识别准确率高,始终保持在70%以上,平均能耗仅为89J。