This study proposes a new generation of floating gate transistors(FGT)with a novel built-in security feature.The new device has applications in guarding the IC chips against the current reverse engineering techniques,...This study proposes a new generation of floating gate transistors(FGT)with a novel built-in security feature.The new device has applications in guarding the IC chips against the current reverse engineering techniques,including scanning capacitance microscopy(SCM).The SCM measures the change in the C–V characteristic of the device as a result of placing a minute amount of charge on the floating gate,even in nano-meter scales.The proposed design only adds a simple processing step to the conventional FGT by adding an oppositely doped implanted layer to the substrate.This new structure was first analyzed theoretically and then a two-dimensional model was extracted to represent its C–V characteristic.Furthermore,this model was verified with a simulation.In addition,the C–V characteristics relevant to the SCM measurement of both conventional and the new designed FGT were compared to discuss the effectiveness of the added layer in masking the state of the transistor.The effect of change in doping concentration of the implanted layer on the C–V characteristics was also investigated.Finally,the feasibility of the proposed design was examined by comparing its I–V characteristics with the traditional FGT.展开更多
The performance of complementary metal oxide semiconductor(CMOS)circuits is affected by electromagnetic interference(EMI),and the study of the circuit's ability to resist EMI will facilitate the design of circuits...The performance of complementary metal oxide semiconductor(CMOS)circuits is affected by electromagnetic interference(EMI),and the study of the circuit's ability to resist EMI will facilitate the design of circuits with better performance.Current-mode CMOS circuits have been continuously developed in recent years due to their advantages of high speed and low power consumption over conventional circuits under the deep submicron process;their EMI resistance performance deserves further study.This paper introduces three kinds of NOT gate circuits:conventional voltage-mode CMOS,MOS current-mode logic(MCML)with voltage signal of input and output,and current-mode CMOS with current signal of input and output.The effects of EMI on three NOT gate circuits are investigated using Cadence Virtuoso software simulation,and a disturbance level factor is defined to compare the effects of different interference terminals,interference signals'waveforms,and interference signals'frequencies on the circuits in the 65 nm process.The relationship between input resistance and circuit EMI resistance performance is investigated by varying the value of cascade resistance at the input of the current-mode CMOS circuits.Simulation results show that the current-mode CMOS circuits have better resistance performance to EMI at high operating frequencies,and the higher the operating frequency of the current-mode CMOS circuits,the better the resistance performance of the circuits to EMI.Additionally,the effects of different temperatures and different processes on the resistance performance of three circuits are also studied.In the temperature range of-40℃to 125℃,the higher the temperature,the weaker the resistance ability of voltage-mode CMOS and MCML circuits,and the stronger the resistance ability of current-mode CMOS circuits.In the 28 nm process,the current-mode CMOS circuit interference resistance ability is relatively stronger than that of the other two kinds of circuits.The relative interference resistance ability of voltage-mode CMOS and MCML circuits in the 28 nm process is similar to that of the 65 nm process,while the relative interference resistance ability of current-mode CMOS circuits in the 28 nm process is stronger than that of the 65 nm process.This study provides a basis for the design of current-mode CMOS circuits against EMI.展开更多
SiC金属-氧化物-半导体场效应晶体管(MOSFET)作为车用电机控制器功率单元的核心器件,其并联不均流问题是影响电机控制器安全稳定运行的关键因素。对于热增强塑料封装(TPAK)SiC MOSFET功率模块实际应用中的不均流问题,首先通过理论推导...SiC金属-氧化物-半导体场效应晶体管(MOSFET)作为车用电机控制器功率单元的核心器件,其并联不均流问题是影响电机控制器安全稳定运行的关键因素。对于热增强塑料封装(TPAK)SiC MOSFET功率模块实际应用中的不均流问题,首先通过理论推导和仿真,对影响SiC并联均流的器件参数、功率回路参数、驱动回路参数进行了全面的分析总结。然后结合仿真结果对电机控制器进行均流优化设计,其中包括对TPAK SiC MOSFET进行测试、筛选和分析,减小器件参数分散性的影响;基于器件开关特性,对功率模块的驱动回路采用单驱动器多推挽结构,减小驱动回路对并联均流的影响;设计了一种叠层母排结构,在ANSYS Q3D中提取到功率回路寄生电感为9.649 nH,采用ANSYS Q3D和Simplorer进行联合双脉冲仿真,电流不均衡度小于3%。最后,进行了电机控制器样机的试制及测试,实际测试结果表明电流不均衡度小于5%,验证了在车用电机控制器应用中TPAK SiC MOSFET模块均流设计的可行性。展开更多
A new approach to reduce the reverse current of Ge pin photodiodes on Si is presented, in which an i-Si layer is inserted between Ge and top Si layers to reduce the electric field in the Ge layer. Without post- growth...A new approach to reduce the reverse current of Ge pin photodiodes on Si is presented, in which an i-Si layer is inserted between Ge and top Si layers to reduce the electric field in the Ge layer. Without post- growth annealing, the reverse current density is reduced to -10 mA/cm^2 at -1 V, i.e., over one order of magnitude lower than that of the reference photodiode without i-Si layer. However, the responsivity of the photodiodes is not severely compromised. This lowered-reverse-current is explained by band-pinning at the i-Si/i-Ge interface. Barrier lowering mechanism induced by E-field is also discussed. The presented ＂non-thermal＂ approach to reduce reverse current should accelerate electronics-photonics convergence by using Oe on the Si complementary metal oxide semiconductor （CMOS） platform.展开更多
文摘This study proposes a new generation of floating gate transistors(FGT)with a novel built-in security feature.The new device has applications in guarding the IC chips against the current reverse engineering techniques,including scanning capacitance microscopy(SCM).The SCM measures the change in the C–V characteristic of the device as a result of placing a minute amount of charge on the floating gate,even in nano-meter scales.The proposed design only adds a simple processing step to the conventional FGT by adding an oppositely doped implanted layer to the substrate.This new structure was first analyzed theoretically and then a two-dimensional model was extracted to represent its C–V characteristic.Furthermore,this model was verified with a simulation.In addition,the C–V characteristics relevant to the SCM measurement of both conventional and the new designed FGT were compared to discuss the effectiveness of the added layer in masking the state of the transistor.The effect of change in doping concentration of the implanted layer on the C–V characteristics was also investigated.Finally,the feasibility of the proposed design was examined by comparing its I–V characteristics with the traditional FGT.
文摘The performance of complementary metal oxide semiconductor(CMOS)circuits is affected by electromagnetic interference(EMI),and the study of the circuit's ability to resist EMI will facilitate the design of circuits with better performance.Current-mode CMOS circuits have been continuously developed in recent years due to their advantages of high speed and low power consumption over conventional circuits under the deep submicron process;their EMI resistance performance deserves further study.This paper introduces three kinds of NOT gate circuits:conventional voltage-mode CMOS,MOS current-mode logic(MCML)with voltage signal of input and output,and current-mode CMOS with current signal of input and output.The effects of EMI on three NOT gate circuits are investigated using Cadence Virtuoso software simulation,and a disturbance level factor is defined to compare the effects of different interference terminals,interference signals'waveforms,and interference signals'frequencies on the circuits in the 65 nm process.The relationship between input resistance and circuit EMI resistance performance is investigated by varying the value of cascade resistance at the input of the current-mode CMOS circuits.Simulation results show that the current-mode CMOS circuits have better resistance performance to EMI at high operating frequencies,and the higher the operating frequency of the current-mode CMOS circuits,the better the resistance performance of the circuits to EMI.Additionally,the effects of different temperatures and different processes on the resistance performance of three circuits are also studied.In the temperature range of-40℃to 125℃,the higher the temperature,the weaker the resistance ability of voltage-mode CMOS and MCML circuits,and the stronger the resistance ability of current-mode CMOS circuits.In the 28 nm process,the current-mode CMOS circuit interference resistance ability is relatively stronger than that of the other two kinds of circuits.The relative interference resistance ability of voltage-mode CMOS and MCML circuits in the 28 nm process is similar to that of the 65 nm process,while the relative interference resistance ability of current-mode CMOS circuits in the 28 nm process is stronger than that of the 65 nm process.This study provides a basis for the design of current-mode CMOS circuits against EMI.
文摘SiC金属-氧化物-半导体场效应晶体管(MOSFET)作为车用电机控制器功率单元的核心器件,其并联不均流问题是影响电机控制器安全稳定运行的关键因素。对于热增强塑料封装(TPAK)SiC MOSFET功率模块实际应用中的不均流问题,首先通过理论推导和仿真,对影响SiC并联均流的器件参数、功率回路参数、驱动回路参数进行了全面的分析总结。然后结合仿真结果对电机控制器进行均流优化设计,其中包括对TPAK SiC MOSFET进行测试、筛选和分析,减小器件参数分散性的影响;基于器件开关特性,对功率模块的驱动回路采用单驱动器多推挽结构,减小驱动回路对并联均流的影响;设计了一种叠层母排结构,在ANSYS Q3D中提取到功率回路寄生电感为9.649 nH,采用ANSYS Q3D和Simplorer进行联合双脉冲仿真,电流不均衡度小于3%。最后,进行了电机控制器样机的试制及测试,实际测试结果表明电流不均衡度小于5%,验证了在车用电机控制器应用中TPAK SiC MOSFET模块均流设计的可行性。
基金supported by the Grant-in-Aid for Creative Scientific Research on Si CMOS Photonics in Japan.The meaeurecl devices were fabricated in the Takeda Sentanchi Facility of the University of Tokyo Japan.
文摘A new approach to reduce the reverse current of Ge pin photodiodes on Si is presented, in which an i-Si layer is inserted between Ge and top Si layers to reduce the electric field in the Ge layer. Without post- growth annealing, the reverse current density is reduced to -10 mA/cm^2 at -1 V, i.e., over one order of magnitude lower than that of the reference photodiode without i-Si layer. However, the responsivity of the photodiodes is not severely compromised. This lowered-reverse-current is explained by band-pinning at the i-Si/i-Ge interface. Barrier lowering mechanism induced by E-field is also discussed. The presented ＂non-thermal＂ approach to reduce reverse current should accelerate electronics-photonics convergence by using Oe on the Si complementary metal oxide semiconductor （CMOS） platform.
