Interference cancellation is made available by using smart antenna at cellular base stations. Well distributed cumulative probability of signal to interference plus noise power ratio appears to be vital for cellular m...Interference cancellation is made available by using smart antenna at cellular base stations. Well distributed cumulative probability of signal to interference plus noise power ratio appears to be vital for cellular mobile multimedia communications. A scenario of dual links dynamic power control combined to a solution of smart antenna is proposed to adjust the instant transmission power in terms of the disparity from the favorite range. Simulation results show that this method is quite effective to improve the cumulative distribution probability performance. Meanwhile, accompanying low power consumption is also obtained at both base stations and mobile stations.展开更多
A low power model for Code Division Multiple Access (CDMA) based cellular communication system is developed. The dynamic power is minimized by reducing the frequency of the Phase Lock Loop (PLL) after lock is establis...A low power model for Code Division Multiple Access (CDMA) based cellular communication system is developed. The dynamic power is minimized by reducing the frequency of the Phase Lock Loop (PLL) after lock is established. The paper addresses the feasibility of lowering the clock frequency of the processing unit that models the PLL is addressed and modulator/demodulator functions of the system while maintaining synchronization with the memory unit and other peripherals. The system is simulated with Matlab considering various Signal-to-Noise Ratios (SNR). For a given SNR, the minimum frequency required for the PLL to maintain lock is determined. The Matlab file is translated to VHDL code, simulated and synthesized with Mentor tools, and the layout then generated. Mach-Pa 5-V software system from Mentor tools is utilized to estimate the power consumed by the simulated device. A Xilinx file is also generated and downloaded for Field Programmable Gate Arrays (FPGA) implementation. A 50 MHz clock frequency of the processing unit was first considered and then lowered to 20 MHz for the low power study. Lowering the base and clock frequency resulted in near 30% reduction in power.展开更多
Power control is an important issue in mobile communication systems and has been studied extensively in the literature. This paper has taken on a new perspective and modeled the problem as a state estimation problem w...Power control is an important issue in mobile communication systems and has been studied extensively in the literature. This paper has taken on a new perspective and modeled the problem as a state estimation problem with finite communication constraints. The problem is solved by using the 1-bit mean coder-estimator sequence. The performance of the coder-estimator sequence is compared with that of the simple feedback power control technique by evaluating their respective fade margins as in commonly done in radio system engineering.展开更多
文摘Interference cancellation is made available by using smart antenna at cellular base stations. Well distributed cumulative probability of signal to interference plus noise power ratio appears to be vital for cellular mobile multimedia communications. A scenario of dual links dynamic power control combined to a solution of smart antenna is proposed to adjust the instant transmission power in terms of the disparity from the favorite range. Simulation results show that this method is quite effective to improve the cumulative distribution probability performance. Meanwhile, accompanying low power consumption is also obtained at both base stations and mobile stations.
文摘A low power model for Code Division Multiple Access (CDMA) based cellular communication system is developed. The dynamic power is minimized by reducing the frequency of the Phase Lock Loop (PLL) after lock is established. The paper addresses the feasibility of lowering the clock frequency of the processing unit that models the PLL is addressed and modulator/demodulator functions of the system while maintaining synchronization with the memory unit and other peripherals. The system is simulated with Matlab considering various Signal-to-Noise Ratios (SNR). For a given SNR, the minimum frequency required for the PLL to maintain lock is determined. The Matlab file is translated to VHDL code, simulated and synthesized with Mentor tools, and the layout then generated. Mach-Pa 5-V software system from Mentor tools is utilized to estimate the power consumed by the simulated device. A Xilinx file is also generated and downloaded for Field Programmable Gate Arrays (FPGA) implementation. A 50 MHz clock frequency of the processing unit was first considered and then lowered to 20 MHz for the low power study. Lowering the base and clock frequency resulted in near 30% reduction in power.
基金Supported by a grant from the Hong Kong Research Grants Councilpartially supported by Shenzhen University
文摘Power control is an important issue in mobile communication systems and has been studied extensively in the literature. This paper has taken on a new perspective and modeled the problem as a state estimation problem with finite communication constraints. The problem is solved by using the 1-bit mean coder-estimator sequence. The performance of the coder-estimator sequence is compared with that of the simple feedback power control technique by evaluating their respective fade margins as in commonly done in radio system engineering.
